Showing papers on "Polycrystalline silicon published in 1990"

The effects of dopants on surface‐energy‐driven secondary grain growth in silicon films

Abstract: The effects of phosphorus, arsenic, and boron on surface‐energy‐driven secondary grain growth (SEDSGG) in thin polycrystalline silicon films have been investigated. At concentrations at or above 5×1020 cm−3, phosphorus and arsenic were found to markedly enhance SEDSGG while boron had little effect. However, codoping with phosphorous and boron or arsenic and boron lead to compensation (reduction or elimination) of the enhancement effect. The kinetics of SEDSGG were analyzed using transmission electron microscopy. In order to identify electronic as well as segregation effects of dopants on the kinetics of SEDSGG, electron concentrations in the Si films were determined from Hall measurements and dopant segregation was directly measured using scanning transmission electron microscopy and energy‐dispersive x‐ray analysis. Analogous to normal grain growth, dopant‐induced enhancement of SEDSGG can be explained in terms of an increased grain‐boundary atomic mobility due to changes in point‐defect concentrations r...

Effect of substrate temperature on recrystallization of plasma chemical vapor deposition amorphous silicon films

Abstract: The effect of substrate temperature on the recrystallization of plasma chemical vapor deposition amorphous silicon films is investigated. The grain size of polycrystalline silicon films recrystallized at 600 °C increases as the substrate temperature decreases. The enlargement in the grain size is attributed to the decrease in the nucleation rate. The nucleation rate is suppressed by an increase in structural disorder of the Si network. Electrical properties of recrystallized films are improved by the increase in the grain size.

A new type of high efficiency with a low‐cost solar cell having the structure of a μc‐SiC/polycrystalline silicon heterojunction

Abstract: A new type of high‐efficiency solar cell has been developed by a simple production process only with electron cyclotron resonance plasma‐assisted chemical vapor deposition of highly conductive microcrystalline silicon carbide (μ c ‐SiC) on polycrystalline silicon (poly‐Si). The device consists of a p ‐type μ c ‐SiC/ n ‐type poly‐Si heterojunction where the window material is a specially made wide‐band gap and highly conductive μ c ‐SiC. At the present stage, a conversion efficiency of 15.4% with V oc=556 mV, J sc=35.7 mA/cm2, and F. F.=77.4% has been achieved. Also employing this device as a bottom cell in a four‐terminal amorphous silicon ( a ‐Si) tandem‐type solar cell, 16.8% efficiency has been obtained. A series of technical data on the fabrication technology and device performance is presented and discussed.

Numerical Simulations of Amorphous and Polycrystalline Silicon Thin-Film Transistors

Abstract: In this paper we present results of two-dimensional numerical simulations of both amorphous silicon and NMOS and PMOS polycrystalline silicon thin-film transistors. Both types of devices are modeled using an effective medium approach whereby the defects and grain boundaries in the material are treated as a spatially uniform density of localized states in the band gap. The field-effect mobility is self-consistently calculated from the appropriate band mobility and using one set of parameters for each material we obtain very good agreement between simulations of both output and transfer characteristics and experimental data. The experimental activation energy of the source-drain current for the polycrystalline devices is also found to be in excellent agreement with the numerical simulations.

Short time electron cyclotron resonance hydrogenation of polycrystalline silicon thin‐film transistor structures

Abstract: Electron cyclotron resonance plasmas have been used to produce the most effective, shortest time plasma hydrogenation of thin‐film polycrystalline silicon transistors yet reported. We demonstrate that significant improvement in device characteristics can be achieved with these plasmas using exposure times of the order of only 1 min and that 5 min exposures give saturated characteristics of a 2 V threshold voltage, a 65 cm2/V s mobility, and a 107 on/off ratio. We also explore the pressure and power level dependence of this passivation, as well as the effects of shielding with a grid, and show that the more efficient and more stable electron cyclotron resonance hydrogen exposures are at lower pressures.

A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors

Abstract: A physical model considering the effects of grain boundaries on the turn-on behavior of polysilicon thin-film transistors (poly-Si TFTs) is presented. Along the channel, the formation of the potential barrier near the grain boundary is proposed to account for the low transconductance and high turn-on voltage of TFTs. The barrier height is expressed in terms of channel doping, gate oxide thickness, grain size, and external gate as well as drain biases. Drain bias results in an asymmetric potential barrier and introduces more carrier injection from the lowered barrier side. It is shown that this consideration is very important for characterizing the saturation region under large drain-bias conditions. On the basis of the developed potential barrier model, the I-V characteristics are described by the interfacial-layer thermionic-diffusion model. Thin-film transistors on polycrystalline silicon with a coplanar structure were fabricated for testing. Comparisons show excellent agreement between the developed model and the experimental data. >

Anisotropic etch method for a sandwich structure

Abstract: A plasma etch process to anisotropically etch a sandwich structure of silicon dioxide, polycrystalline silicon, and silicon dioxide "in situ", that is, in a single etch chamber The silicon dioxide is etched using a SF 6 /CHF 3 /He chemistry The polycrystalline silicon is etched using a HBr/He chemistry A non-erodible cathode is used Tungsten silicide may replace the polycrystalline silicon Silicon nitride may replace the silicon dioxide

Preparation of High-Quality n-Type Poly-Si Films by the Solid Phase Crystallization (SPC) Method

Abstract: For further improvement of conversion efficiency in a-Si solar cells, it is necessary to develop materials with high photosensitivity in the long-wavelength region. A new solid phase crystallization (SPC) method was developed to grow a Si crystal at temperatures as low as 600°C. Using this method, high-quality thin-film polycrystalline silicon (poly-Si) with a Hall mobility of 70 cm2/Vs was obtained. Quantum efficiency in the range of 800 nm ~ 1000 nm was achieved up to 80% in an experimental solar cell using the n-type poly-Si with a grain size of about 1.5 µm. Therefore, it was found that our SPC method was suitable as a new technique to prepare high-quality solar cell materials.

Doping and crystallographic effects in Cl‐atom etching of silicon

Abstract: Absolute rates for the intrinsic reaction between Cl atoms and surfaces of P‐doped polycrystalline silicon, P‐doped Si(100) and As, Sb‐doped Si(111) substrates were measured for the first time as a function of dopant concentration (Ne) and substrate temperature in a downstream reaction system. This study clearly shows that when there is no ion bombardment, increasing Ne increases the Si‐Cl reaction rate even when silicon is lightly doped (∼1015 cm−3), in contrast to in‐discharge studies. Moreover, results showed that crystal orientation influences the Cl‐Si reaction more than Ne, for Ne<1020 cm−3. The data are fitted to a modified Arrhenius expression, R=νNγenClT1/2e−E/kT, with R the etch rate and nCl the gas phase Cl concentration. The calculated values of the activation energy E are 4.1–4.7 kcal/mole for all doping levels and crystallographic orientations. Therefore, the doping effect is manifested solely in the preexponential (νNγe) of the Arrhenius expression, and the data qualitatively agree with a charge‐transfer mechanism which facilitates chemisorption of chlorine.

Model for the above-threshold characteristics and threshold voltage in polycrystalline silicon transistors

Abstract: A new theory of polycrystalline silicon thin‐film transistors is proposed, based on a continuous trap state density. Three different regimes are predicted: subthreshold, transitional, and crystallinelike. Two characteristic voltages are identified: the threshold voltage, corresponding to the condition of equal trapped and free charge concentration at the oxide/semiconductor interface and the on‐voltage, corresponding to the condition of equal trapped and free charge in the whole space‐charge region. In the case of an exponential distribution of gap states, approximated analytical expressions can be deduced and a simple accurate fitting procedure is presented. A very good agreement with the experiment is obtained, confirming the importance of taking into account the detailed energy dependence of the trap distribution.

17.8-percent efficiency polycrystalline silicon solar cells

Abstract: A substantial increase to 17.8% in the efficiency of cast polycrystalline solar cells was achieved by incorporating phosphorus pretreatment and rear aluminium treatments into the passivated emitter solar cell (PESC) sequence. The deleterious effects of grain boundaries and defects were nullified to such an extent that the performance of cells produced on the less-expensive polycrystalline material of medium grain size matched the performance of those fabricated on expensive semiconductor-grade substrates. Surface texturing of polycrystalline solar cells by novel approaches appears feasible, with a corresponding 5% relative performance increase anticipated, as observed with crystalline cells. >

Design properties of polycrystalline silicon

Abstract: Polycrystalline silicon is used in a variety of sensor applications, in which stress and other mechanical effects can dominate the device behavior. The

Method of manufacturing thermopile infrared detector

Abstract: A thermopile detector is disclosed consisting of a semiconductor supporting rim which is doped across all of the rim. The rim supports a series of polycrystalline silicon and metal thermocouples. The fully doped semiconductor area serves as an etch stop for a single-sided etch which eliminates the need for front-to-back alignment of the device. The semiconductor doped rim also serves as a good thermal condutor for supporting the cold junctions. The hot junctions of the thermocouples may be supported by a thin dielectric membrane spanning the device and the cold junctions are formed on the doped rim. The thin dielectric window provides thermal isolation between the semiconductor rim and the center of the window where the hot junctions are located. The thermocouple material layers may be stacked to enable greater thermocouple denisty on the device. Refractory metals may be employed as the thermocouple metal, to increase sensitivity.

Method of making a non-volatile memory cell utilizing polycrystalline silicon spacer tunnel region

Abstract: A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

Rapid thermal chemical vapor deposition of germanium on silicon and silicon dioxide and new applications of Ge in ULSI technologies

Abstract: In this study, low pressure chemical vapor deposition of pure germanium on silicon and silicon dioxide has been considered for new applications in future ultra large scale integration (ULSI) technologies. Germanium depositions were performed in a lamp heated cold-wall rapid thermal processor using thermal decomposition of GeH4. It is shown that Ge deposition on Si can be characterized by two different regions: a) at temperatures below approximately 450° C, the deposition is controlled by the rate of surface reactions resulting in an activation energy of 41.7 kcal/mole. b) Above this temperature, mass transport effects become dominant. The deposition rate at the transition temperature is approximately 800 A/min. It is shown that Ge deposition on SiO2 does not occur, even at temperatures as high as 600° C, resulting in a highly selective deposition process. Selectivity, combined with low deposition temperature makes the process very attractive for a number of applications. In this work, it is shown for the first time that selective Ge deposition can be used to eliminate silicon consumption below the gate level during the silicidation of the shallow source and drain junctions of deep submicron MOSFETs. In addition, a new in situ technique has been developed which allows polycrystalline germanium (poly-Ge) deposition on SiO2. In this work poly-Ge has been considered as a low temperature alternative to polycrystalline silicon (poly-Si) in the formation of gate electrodes in single-wafer manufacturing where low-thermal budget processes are most desirable.

Thin-film transistor

Abstract: PURPOSE:To obtain a good contact between a semiconductor layer and electrode wiring even when the thickness of the semiconductor layer is reduced by separating a source-drain area from a gate electrode after simultaneously forming the source-drain area and gate electrode and connecting the source-drain area with electrode wiring through a polycrystalline silicon film which is reduced in resistance. CONSTITUTION:An electrode contacting member 9 which is separated from a gate electrode 5 and produced from the same polycrystalline silicon film as that used for the gate electrode 5 by reducing the resistance by patterning is provided in a source-drain area 8 and, at the same time, an insulating film 3 formed on a semiconductor layer 2 is patterned so that the film 3 can be left below the gate electrode 5 only. Moreover, electrode wiring 7 is brought into contact with the source-drain area 8 through the electrode contacting member. 9. Therefore, a good contact can be obtained with a wiring material even when the thickness of the semiconductor layer 2 is reduced.

DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance

Abstract: A DRAM cell having enhanced capacitance attributable to the use of a textured polycrystalline silicon storage-node capacitor plate (65). The present invention is particularly applicable to DRAM cells which employ a stacked-capacitor design, as such designs generally a conductively-doped polycrystalline silicon layer as the storage-node, or lower, capacitor plate. A poly texturization process imparts a three-dimensional texturized character to the upper surface of a first polysilicon layer (57). Texturization of this layer is accomplished by subjecting it to a wet oxidation step. Since oxidation at the crystal grain boundaries on the surface of first poly layer (57) proceeds more rapidly than elsewhere, the surface becomes bumpy. When maximum texturization has been achieved, the overlying oxide (59) is removed from first poly layer (57) during a wet etch step. With texturization complete, first poly layer (57) is patterned to form a storage node plate (65). A thin (70-100 angstroms thick) silicon nitride layer (67) is deposited on top of storage node plate (65), followed by the deposition of a second poly layer (69), which, after patterning, functions as the capacitor field plate. Since the nitride layer (67) is thin in comparison to the bumps on the surface of the storage-node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased approximately thirty percent using a storage-node plate so texturized.

Method of fabricating an improved polycrystalline silicon thin film transistor

Abstract: A process of fabricating an improved transistor on a polycrystalline silicon layer, wherein N and P type dopants, in approximate equal concentrations, are introduced into the layer, and the layer heated. The resultant modified polycrystalline silicon layer inhibits the migration of dopants, used to form the active regions of the device, during subsequent heating steps. An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.

Theory of grain boundary recombination and carrier transport in polycrystalline silicon under optical illumination

Abstract: The physics controlling the recombination of minority carriers at grain boundaries in polycrystalline silicon under optical illumination is described theoretically, and a model for the grain boundary space-charge potential barrier height is presented. The model is based on the assumption of a Gaussian energy distribution of grain boundary interface states. Attention is also focused on the electrical conduction in this material under illumination. The dependence of space-charge potential barrier height and the effective recombination velocity on the illumination level, the grain size, and the bulk diffusion length of minority carriers (L/sub b/) is investigated. Computations show that if the illumination level is high, the sensitivity of effective recombination velocity to grain size (d) in the intermediate grain size range (i.e. d approximately=L/sub b/) is much higher than that in the small and large grain size ranges. It is found that the resistivity of polysilicon decreases on increasing illumination level. The dependence of polysilicon resistivity on grain size under optical illumination is found to be much higher than that under dark conditions. >

Selective deposition of polycrystalline silicon

Abstract: A method for selectively depositing polysilicon on a semiconductor surface (13) is accomplished by preparing the surface (13) in a manner to provide a contamination free surface. The contamination free semiconductor surface is placed into a chemical vapor deposition reactor. The semiconductor surface (13) is exposed to a single crystal inhibitor gas to prevent formation of single crystal silicon on surface (13). Semiconductor surface (13) is then exposed to a silicon containing gas with a hydrogen source to form the polysilicon.

Fabricating method for silicon devices using a two step silicon etching process

Abstract: Disclosed is a method of fabricating a precision etched, three dimensional device from a silicon wafer, wherein the etching is done from one side of the wafer using a two step silicon etching process. A two-sided deposition of a robust protective layer, such as polycrystalline silicon, is placed over a two-sided deposition of a chemical masking layer such as silicon dioxide. The two layers are concurrently patterned with first and second sets of vias on one side of the wafer, while the opposite side is protected by the protective layer. The protective layer is removed to permit deposition of a second masking layer such as silicon nitride, followed by deposition of a second protective layer. Again, the second protective layer prevents damage to the fragile second masking layer on the wafer backside while its frontside is patterned with a similar set of vias aligned with the first set of vias in the first masking layer. This similar set of vias is sequentially formed in both the second protective layer and the underlying second masking layers. Then the wafer is placed in an etchant bath so that the first set of recesses is anisotropically etched in the wafer frontside side. Next, the second protective layer and second masking layer are removed to permit anisotropic etching of the second set of recesses through the second set of vias in the first masking layer. If the protective layer is polycrystalline silicon, it is concurrently etch-removed during the initial etching of the silicon wafer.

High Efficiency Crystalline Silicon Solar Cells

Abstract: The efficiency of crystalline silicon solar cells under non concentrated light has increased since 1983 from 17% to over 23%, a large gain for a relatively mature technology Improvements have been made in several areas, notably in the trapping of weakly absorbed infra red radiation within the silicon, in surface passivation and in maintenance of high carrier lifetimes during processing These and other improvements are discussed, and it is concluded that efficiencies of 25% are possible with current technology However, improved methods of surface passivation are required for further progress towards the limit for conventional cells of around 29% There has also been significant progress in efficiencies on lower cost polycrystalline silicon substrates to close to 18% Cells with efficiencies above 20% seem possible by adapting the high efficiency techniques mentioned above to thin polycrystalline substrates Crystalline silicon remains the most attractive semiconductor for solar cell applications

Fluidized bed for production of polycrystalline silicon

Abstract: An improved fluidized bed reactor and a method for utilizing the fluidized bed reactor in the production of, for example, high purity polycrystalline silicon, by the pyrolysis of silane containing gas. The reactor being characterized by an entrainment zone located above a lower reaction zone. The entrainment zone having a cross-sectional area less than or equal to the cross-sectional area of the reaction zone and being capable of maintaining a fluidization gas velocity sufficient to entrain silicon powder particles, yet not sufficient to entrain silicon particles.

Recrystallization and grain growth phenomena in polycrystalline Si/CoSi2 thin‐film couples

Abstract: This paper presents high‐temperature effects on CoSi2/polycrystalline silicon (poly‐Si) bilayers, intended for metal‐oxide‐semiconductor gate applications. Both rapid thermal annealing and conventional furnace annealing were utilized for the investigation. At temperatures above 700 °C the structure breaks down due to silicon recrystallization within the silicide and simultaneous silicide growth into the polycrystalline silicon film. Recrystallized silicon adopts the silicide texture and this process terminates when the entire polysilicon layer is consumed. After completion the layer configuration is inverted, i.e., the silicide is adjacent to the gate oxide and covered with elemental silicon at the surface. This surface layer consists of large grains with few crystal defects, very different from the columnar structure of the as‐deposited silicon. With further annealing, grain growth in both phases continues, and each grain will ultimately extend from the oxide interface to the free surface. Lateral grain ...

An analytical model for 1/f noise in polycrystalline silicon thin films

Abstract: Noise calculations based on Hooge's empirical mobility fluctuation model are presented for mobility fluctuations occurring in the quasi-neutral and the depletion-barrier regions of low to moderately doped polycrystalline silicon resistors. Comparing the theoretical predictions with the experimental results, it is concluded from the bias dependence and the magnitude of the noise density that the 1/f noise in polysilicon is depletion-region dominant. The limiting role of grain boundaries, the noise correlation between depletion regions on both sides of a grain boundary, and a noise source weight function are taken into account. The Hooge parameter found from the model and data is 1.45*10/sup -3/. >

Method of making a sidewall contact

Abstract: A semiconductor device comprises a P-type semiconductor substrate having a major surface, an insulating film formed on the major surface of the semiconductor substrate, a first polycrystalline silicon layer formed on the insulating film, an n + diffused layer formed on the substrate and adjacent to an end portion of the first polycrystalline silicon layer, and a side wall formed on the end portion of the first polycrystalline silicon layer and formed of a second polycrystalline silicon layer for connecting the end portion of the first polycrystalline silicon layer with the n + diffused layer.

Radiation resistant passivation of silicon solar cells

Abstract: The interface of a silicon oxide passivation layer and a silicon substrate in a silicon solar cell is stabilized by covering the silicon oxide passivation layer with a layer of undoped or phosphorus doped polycrystalline silicon. A second layer of silicon oxide is formed by deposition on the surface of the phosphorus doped polycrystalline and enhances the anti-reflection characteristics of the composite structure.

Method for manufacturing a DRAM using selective epitaxial growth on a contact

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce ion channeling effect by forming a polycrystalline silicon gate electrode, oxidizing the surface of a gate electrode, then depositing an amorphous silicon film, then ion implanting and then removing the amorphous silicon film by etching. CONSTITUTION:A body of a semiconductor substrate 3 is prepared, heat treated to provide a gate oxide film 2, a polycrystalline silicon film is deposited thereon, phosphorus is doped on the silicon film to reduce its resistance value, and a gate electrode 1 is formed by etching. Then, an amorphous silicon film 4 is deposited. Subsequently, in order to form a source.drain diffused layer on the substrate 3, impurity ions are implanted to the board 3 through the films 4, 2 with an ion beam 5. Further, the film 4 is removed by etching. Thereafter, it is annealed to activate the impurity implanted to the substrate 3 to form a source.drain diffused region 6.