Showing papers on "Polycrystalline silicon published in 1991"

Stress‐related problems in silicon technology

Abstract: The silicon integrated‐circuits chip is built by contiguously embedding, butting, and overlaying structural elements of a large variety of materials of different elastic and thermal properties. Stress develops in the thermal cycling of the chip. Furthermore, many structural elements such as CVD (chemical vapor deposition) silicon nitride, silicon dioxide, polycrystalline silicon, etc., by virtue of their formation processes, exhibit intrinsic stresses. Large localized stresses are induced in the silicon substrate near the edges and corners of such structural elements. Oxidation of nonplanar silicon surfaces produces another kind of stress that can be very damaging, especially at low oxidation temperatures. Mismatch of atomic sizes between dopants and the silicon, and heteroepitaxy produce another class of strain that can lead to the formation of misfit dislocations. Here we review the achievements to date in understanding and modeling these diverse stress problems.

Hydrogen in semiconductors

Abstract: :N. H. Nickel, Introduction to Hydrogen in Semiconductors II. Noble M. Johnson and Chris G. Van de Walle, Isolated Monatomic Hydrogen in Silicon. Yu. V. Gorelkinskii, Electron Paramagnetic Resonance of Hydrogen and Hydrogen-Related Defects in Crystalline Silicon. N. H. Nickel, Hydrogen in Polycrystalline Silicon. W. Beyer, Hydrogen Phenomena in Hydrogenated Amorphous Silicon. Chris G. Van de Walle, Hydrogen Interactions with Polycrystalline and Amorphous Silicon-Theory. K. M. McNamara Rutledge, Hydrogen in Polycrystalline CVD Diamond. R. L. Lichti, Dynamics of Muonium Diffusion, Site Changes and Charge-State Transitions. Matthew D. McCluskey and Eugene E. Haller, Hydrogen in III-V and II-VI Semiconductors. S. J. Pearton and J. W. Lee, The Properties of Hydrogen in GaN and Related Alloys. Jorg Neugebauer and Chris G. Van de Walle, Theory of Hydrogen in Ga N.

Surface micromachined pressure transducers

Abstract: Typical IC processing is fundamentally two dimensional; sensors are three-dimensional structures. In surface micromachining, two-dimensional IC processing is extended to sensor structures by the addition of one or more sacrificial layers which are removed by lateral etching. The resulting sensor structures involve the substrate and one or more deposited films which form the intended micromechanical component. The concepts of this type of sensor manufacturing are readily demonstrated by considering absolute pressure transducers in some detail. Absolute pressure transducers involve a vacuum-sealed cavity and a deformation sensing technique. The cavity is formed from the substrate and a low-pressure chemical vapor deposited polycrystalline silicon film. The mechanical properties of this film must be controlled well enough to allow the device to be designed. This implies morphological control during processing. Optimized films which do exhibit controlled compressive or tensile strains exclude oxygen or nitrogen and are therefore not modified by extended hydrofluoric acid etches. Their mechanical behavior is monitored by micromechanical test structures which measure Euler buckling and thereby determine the value of the built-in strain. The cavity vacuum is established by reactive sealing. Long-term vacuum integrity is achieved by a low-stress silicon nitride barrier which also acts as a dielectric isolation barrier. Sensing is accomplished via deposited polysilicon resistors. These devices behave like metal resistors in terms of their temperature coefficient of resistance and noise figure. Their piezoresistive behavior is larger than that of typical metal film structures and smaller than that of single-crystal resistors. Pressure sensors with four diaphragms, two active and two inactive, have been constructed and optimized towards manufacturability. The measured performance is excellent and agrees with the predictions of the design algorithm.

Piezoresistive pressure sensors based on polycrystalline silicon

Abstract: Polycrystalline Si (poly-Si) has found various applications in microelectronics and micromechanical devices such as pressure sensors, accelerometers and actuators. Poly-Si films deposited on an oxidized Si substrate can combine the excellent mechanical properties of Si with the efficient electrical insulation of poly-Si piezoresistors, so that improved stability and high-temperature operation can be obtained. Different poly-Si fabrication techniques are reviewed with emphasis on their applications to pressure sensors. The theoretical interpretation and models of the piezoresistivity in poly-Si and experimental results are presented. The calculation of the longitudinal and transverse gauge factors and their correlation with the crystallographic structure of the poly-Si film are discussed. The possibility of sensor performance optimization including mechanical, temperature and piezoresistive properties of a device is demonstrated. Two examples of commercially manufactured poly-Si sensors and an example of a new poly-Si technology are also presented.

Method for fabricating polycrystalline silicon having micro roughness on the surface

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.

Enlargement of Poly-Si Film Grain Size by Excimer Laser Annealing and Its Application to High-Performance Poly-Si Thin Film Transistor

Abstract: By both numerical simulation and experimental investigation, we found it possible to enlarge the grain size (?3000 ?) of polycrystalline silicon (poly-Si) films by excimer laser annealing, using a new method to control the solidification process of molten Si - low-temperature (?400?C) substrate heating during laser annealing. Poly-Si thin-film transistors (TFTs) fabricated by this new excimer laser annealing method showed a high field-effect mobility of 230 cm2/V?s, and good uniformity of field-effect mobility (?10%) within the effective laser irradiation area.

Surface‐micromachined PbTiO3 pyroelectric detectors

Abstract: Lead titanate (PbTiO3) thin‐film pyroelectric infrared detectors have been fabricated on polycrystalline silicon micromechanical membranes. Pyroelectric PbTiO3 thin films of thickness ranging from 0.2 to 0.6 μm were prepared by sol‐gel spin casting techniques and deposited on 1.0‐μm‐thick polycrystalline silicon membranes suspended 1.0 μm above the surface of a silicon wafer. This composite structure offers high sensitivity and low thermal mass. The measured pyroelectric coefficient for 0.36‐μm‐thick PbTiO3 films is 90 nC/cm2 K. The measured blackbody voltage responsivity for a pyroelectric element with an active area of 7×10−4 cm2 at 297 K and a chopping frequency of 50 Hz is 4.2×104 V/W. The measured normalized detectivity D* at 297 K and 50 Hz is 1.0×109 cm Hz1/2/W.

Structural properties of polycrystalline silicon films prepared at low temperature by plasma chemical vapor deposition

Abstract: Evolution with thickness of the structure of the polycrystalline silicon (poly‐Si) films prepared at 300 °C has been studied by plasma decomposition of SiF4/SiH4/H2 source gases. The poly‐Si films with varied thickness are characterized mainly by Raman spectroscopy, x‐ray diffraction (XRD), and supplementarily by reflection high‐energy electron diffraction, transmission electron microscopy, Fourier‐transform infrared (FT‐IR) spectroscopy, electron‐spin resonance (ESR), and secondary‐ion‐mass spectroscopy (SIMS) measurements. The crystalline fraction of the film was calculated to be 87% by deconvoluting the Raman spectra. The grains indicated a strong 〈110〉 preferred orientation by XRD. The thickness (d) dependence of the diffracted (220) intensity is divided into three regions: an incubation region (d<200 nm, region 1), a linear region (200 nm ≤d<300–500 nm, region 2) where the deposition parameter (SiF4 flow rate, substrate temperature, and rf power) dependence is weak, and a linear region with steeper (or more moderate) slopes (300–500 nm≤d, region 3) where the deposition parameter dependence is large. The measurements of the angular distribution of the 〈110〉 grains reveal that they contain slanting ones by more than 4° in region 2, while they disappear in region 3. The FT‐IR and SIMS measurements for typical samples (Ts = 300 °C, 300 Pa) indicate that the grain boundaries are passivated by hydrogen in the bonding configurations of Si—Hn (n=1–3) and its concentration is approximately 3 at. %. The residual fluorine in the film is found to be much fewer (6×1019 cm−3) than hydrogen. It is found that the density of unpassivated dangling bonds indicates a low value of 1.1×1017 cm−3 for the film with d=280 nm by ESR measurements. The origin of the preferred orientation is also discussed on the basis of a model in which nucleation, ledge formation, and etching processes are considered.

High-voltage planar devices using field plate and semi-resistive layers

Abstract: An improved high-voltage technique based on the use of a field plate combined with semiresistive layers (SIPOS) on oxide is proposed. The field plate and SIPOS (semi-insulating polycrystalline silicon) are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second high-resistivity SIPOS layer provides an excellent passivation, and also prevents the dielectric breakdown of the underlayer SIPOS film. Moreover, the savings in chip area is about 20% compared to the standard mesa termination. The global yield is 94% for the SIPOS planar transistors and 86% for equivalent devices in mesa technology. The complete fabrication, design, electrical characteristics, and reliability of high-voltage planar transistors are described. >

Thin film semiconductor device having inverted stagger structure, and device having such semiconductor device

Abstract: TFTs with an inverted stagger structure are fabricated according to the invention as follows; a glass substrate after depositing amorphous silicon (a-Si) thereupon is transferred to a laser annealing chamber which is kept in non-oxidation ambient and provided with a sample holder and a substrate heating mechanism. The substrate is fixed on the sample holder, then subjected to laser annealing while being heated from the glass substrate side, thereby growing polycrystalline silicon having substantially improved crystallinity, on which a-Si is further deposited. According to this process of the invention, it is capable of forming TFTs having a higher mobility and a smaller leakage current in the periphery of the substrate, with addition of almost no changes to the process and device structures of conventional TFTs which constitute pixels, and even more the peripheral drive circuitry is capable of being integrated in the display substrate.

Manufacturing method of non-volatile semiconductor memory device

Abstract: Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.

Manufacture of semiconductor device

Abstract: PURPOSE:To make it possible to form an insulating film having a superior buried flatness and to contrive to improve the yield of the manufacture of an integrated circuit device because the insulating film having the superior flatness can be formed by a process only of one time by a method wherein a deposited film in a fluid state is vapor-phase grown on the main surface of a semiconductor substrate at a substrate temperature equal to an higher than the glass transition temperature of the deposited film. CONSTITUTION:In the manufacturing process of a semiconductor device, wherein a deposited film 204 is formed for flattening a step of the main surface of a semiconductor substrate, the film 204 in a fluid state is vapor-phase grown on the main surface of the substrate using a substrate temperature of the glass transition temperature or higher of the film 204. For example, an insulating film 202 is formed on a single crystal silicon substrate 201 with an semiconductor element formed thereon and moreover, polycrystalline silicon wirings 203 are formed. Then, a vapor growth of a fluid BPSG film 204 is performed at a substrate temperature of 900 deg.C, at a pressure of 0.6 Torr, at the flow rate of 120SCCM of SiH4 gas, at the flow rate of 2 slm of N2O gas, at the flow rate of 10SCCM of PH3 gas and the flow rate of 10SCCM of B2H6 gas. Thereby, the formed film 204 becomes one having a flatness superior that of a conventional film obtainable by performing two processes of film formation and reflow.

Simple integral screenprinting process for selective emitter polycrystalline silicon solar cells

Abstract: This letter describes a new simple fabrication process, developed recently for ‘‘blue response’’ improvement in low‐cost polycrystalline silicon solar cells. A selective emitter is created by heavily doping the emitter, followed by a wet etching‐back of the cell area between the fingers. An improvement up to 17 mV in Voc, 1.5 mA/cm2 in Jsc, and 1% (absolute value) in η is obtained. Effective phosphorus gettering, self‐alignment, and application in a low‐cost full screenprinting technology are the main advantages of the proposed process.

Process for making planarized sub-micrometric trenches in integrated circuits

Abstract: The process comprises the sequential formation, on a silicon substrate (1), of a lower layer (2) of silicon oxide, of an intermediate layer (3) of silicon nitride and of an upper layer (4, 15) of polycrystalline silicon or of silicon oxide, followed by the etching of the latter for the definition of a window (5, 16) having a width greater than that of the desired trench (8). The window (5, 16) is then narrowed down to the width of the desired trench (8) accomplishing some spacers (11) or oxidizing the layer of polycrystalline silicon (15). There is then executed the etching of the substrate (1) inside said narrow window (7, 14, 18) for the accomplishment of the trench (8), followed by the oxidation of the walls of the trench (8) and by its selfplanarization.

Methods for texturizing polysilicon utilizing gas phase nucleation

Abstract: A process for texturization of polycrystalline silicon comprising the steps of utilizing gas phase nucleation by injecting a material to a cause heterogeneous nucleation or by increasing deposition temperature or pressure to cause a homogeneous nucleation of the silicon source itself. Heterogeneous or homogeneous gas phase nucleation causes large, stable textures in the deposited polysilicon that can be doped using conventional fabrication techniques.

Manufacture of semiconductor device

Abstract: PURPOSE:To strengthen the bonding power on the polycrystalline silicon/silicide interface for preventing the release from occurring by a method wherein, after doping the polycrystalline silicon with an impurity, a natural oxide film is etched away within a silicide deposition device to deposit the silicide continuously without exposing it to the atmosphere CONSTITUTION:After forming a gate oxide film on a silicon substrate, a polycrystalline silicon film 3 is deposited to be doped with an impurity however, a spontaneous oxide film 4 is deposited on the polycrystalline silicon This natural oxide film 4 causing the release of silicide shall be removed Thus, the spontaneous oxide film is removed within a silicide depositing device to deposit the silicide continuously without exposing it to the atmosphere In order to remove the spontaneous oxide film 4, HF vapor is suitable but carbon halogenide, sulfur base gas are also applicable The polycide gate thus formed having the high bonding power on the polycrystalline silicon/cilicide interface shall be subjected to no release at all even after the later heat treatment and oxidization processes

Method for manufacturing capacitor of highly integrated semiconductor memory device

Abstract: A method for manufacturing a capacitor of a highly integrated semiconductor memory device including a plurality of memory cells, each of which has a transistor and a capacitor. The method comprises the steps of forming an insulating layer for insulating the transistor, forming a contact hole to electrically connect to a source region by etching the insulating layer, sequentially forming a first polycrystalline silicon layer, an oxide layer, and a second polycrystalline silicon layer consisting of grains, exposing the second polycrystalline silicon layer to an oxide etchant, partially etching the oxide layer by the oxide etchant penetrating along the peripheries of the grains, anistropically etching the whole second polycrystalline silicon layer and, at the same time, the partial first polycrystalline silicon layer also, using the oxide layer being unaffected by the oxide etchant, as a mask, removing the oxide layer, forming a storage electrode by defining into cell units the first polycrystalline silicon layer, sequentially forming a dielectric film and a plate electrode formed of a third polycrystalline silicon layer over the resultant structure. Thus, the physical properties of the material itself is used without any specific conditions and unrestricted by limitation of minimum feature size. Furthermore, the process is greatly simplified and the effective capacitance of the cell capacitor is easily extended.

Fluid flow sensor with thermistor detector

Abstract: An airflow sensor formed on a silicon chip comprises a silicon base covered with an insulating polyimide layer, a lineal resistance heater on the chip energized with current pulses to propagate thermal waves, and a thermistor on the chip downstream of the heater to detect the arrival of each thermal wave. Circuitry determines flow rate as a function of the measured propagation time of the thermal wave. The thermistor may be replaced by a bridge of four resistive elements of which only one or two are sensitive to the thermal wave. The thermistor material is platinum, polycrystalline silicon or amorphous silicon which exhibit high temperature coefficients of resistance.

Thermal inkjet printhead structure and method for making the same

Abstract: An improved thermal inkjet printhead having MOSFET drive transistors incorporated therein. The gate of each MOSFET transistor is formed by applying a layer of silicon dioxide onto a silicon substrate, applying a layer of silicon nitride onto the silicon dioxide, and applying a layer of polycrystalline silicon onto the silicon nitride. Portions of the substrate surrounding the gate are oxidized, forming field oxide regions. Drain and source regions are then conventionally formed, followed by the application of a protective dielectric layer onto the field oxide, drain, source, and gate. A resistive layer is deposited on the dielectric layer and directly connected to the source, drain, and gate. A conductive layer is deposited on a portion of the resistive layer, ultimately forming both covered and uncovered regions thereof. The uncovered region functions as a heating resistor, and the covered regions function as electrical contacts to the transistor and resistor.

Manufacture of semiconductor device

Abstract: PURPOSE:To eliminate the diffusion of impurities into a substrate from a BPSG film and also to eliminate decrease of impurities from a diffused layer by a method wherein a first insulating film is formed on a semiconductor substrate, a BPSG film is formed thereon, and after the pattern of a contact hole has been formed and a fluidizing treatment has been conducted, the whole surface is etched, and the shape after the fluidizing treatment is transferred to the first insulating film. CONSTITUTION:A silicon oxide film is formed on the surface of a P-type silicon substrate 1, a polycrystalline silicon film 3 is deposited thereon, and after a mask M is formed and phosphorus is ion-implanted, a PSG film 10, for example, is formed as a first insulating film. Subsequently, a PSG film 5 is formed in the thickness almost same as the PSG film. Contact holes 6 and 6 are formed on said film 5, a fluidizing treatment is conducted on the BPSG film, the shape of the contact holes is gently sloped, And at the same time, an overall etching is conducted in the thickness of the T1 component as shown in the diagram using a RIE method after an impurity diffusion layer has been formed, the surface of the substrate is exposed, and the shape of the contact holes of the PSG film is transferred in the state as it is. According to this method, phosphorus and boron are not diffused into the substrate when the fluidizing treatment is conducted, and the oxidizing treatment to be conducted on the contact region surface is unnecessitated.

Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surface

Abstract: A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.

Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator

Abstract: Low temperature (T600°C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO2 gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm2/Vs and on/off current ratios greater than 107.

Energy Pay-Back Time of Photovoltaic Modules

Abstract: The energy invested in photovoltaic modules has been investigated on the basis of currently operating commercial production lines in France. The analysis was made for two types of solar cells, polycrystalline silicon and amorphous silicon. The energy which was calculated in this way was compared with the energy produced by these modules under operating conditions in various European climates. An average energy pay-back time of 1.2 years for amorphous silicon modules and 2.1 years for crystalline silicon modules was found. It can be anticipated that these energy pay-back times will decrease in the future.

PMOS transistors in LPCVD polycrystalline silicon-germanium films

Abstract: P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature ( >

Methods for texturizing polysilicon

Abstract: A process for texturization of polycrystalline silicon comprising the steps of preparing the wafer surface prior to poly deposition with a material which will cause the poly to preferentially nucleate during deposition and form poly nodules on the wafer surface. Polysilicon will continue to coat the previously created poly nodules throughout poly deposition, thereby resulting in a stable, texturized polysilicon structure.

High-resolution electron microscopy of diamond hexagonal silicon in low pressure chemical vapor deposited polycrystalline silicon

Abstract: Thin poly-Si layers deposited at 625 °C by LPCVD that are used in silicon technology for microelectronics exhibit a pronounced additional x-ray diffraction peak at about 0.334 nm. High-resolution electron microscopy (HREM) reveals that this peak stems from {010} reflections of a diamond hexagonal (dh) Si phase, which occurs as small inclusions with the orientation relationship (01) ‖ (0001), [011] ‖ [20] to the diamond cubic (dc) Si matrix. Due to the high density of planar faults on {111}, the dh-Si phase also exists in the form of the 2H silicon polytype with the orientation relationship (1) ‖ (0001), [011] ‖ [20]. In the first case the formation of the dh-Si phase may be understood by a multiple twinning transformation process, and in the second case by glide of Shockley partial dislocations on {111} planes. Various other hexagonal polytypes occur, which have all the {010} reflections in common and make a major contribution to the 0.334 nm peak. The medium temperature of 625 °C for layer deposition leads to a 〈011〉 preferential orientation and a high density of twins as well as to high compressive stress in the poly-Si layer itself. This seems to promote the formation of dh-Si. The strong twinning behavior produces a typical tilt grain boundary between adjacent dh-Si grains: [20], (016), Θ = 35°with a translation vector t = 1/2[031] parallel to it. The dh-Si phase vanishes in this poly-Si film after annealing at temperatures above 1000 °C due to grain growth by recrystallization.

Manufacture of semiconductor device

Abstract: PURPOSE:To lessen the number of processes by a method wherein the surface of a semiconductor substrate consisting of some one of laminated wafers is shaved off so as to leave a necessary thickness at the bonding part of the substrate with an intrinsic base and a single crystal is buried in a hole formed by anisotropic etching. CONSTITUTION:A P-type single crystal substrate 3 is prepared, oxide layers 2 and 4 are arranged so as to come into contact with each other and an electrostatic contact bonding is performed. Then, a hole, which passes through the layers 2 and 4 and reaches the P-type Si substrate 3, is opened by anisotropic etching and this hole is filled with a single crystal Si film 5 by an epitaxial growth. The silicon film 5 deposited on a place other than this hole is removed. An emitter window is opened in an oxide layer 11 by anisotropic etching. An oxide layer 21 is etched to form an emitter diffusion window. A polycrystalline silicon film 22 is deposited in the vicinity of this window, an annealing is performed to form a P-N-P transistor and an N-type emitter diffused region 9, a P-type diffused region 10 and a collector contact compensation diffused region 8 are simultaneously formed. Thereby, a bipolar transistor structure can be manufactured in a process of the number of few processes.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent decrease of the impurity concentration of an impurity diffusion layer, and to inhibit increase of the contact resistance of the impurity diffusion layer and a tungsten silicide by nitriding polycrystalline silicon and depositing the tungsten silicide. CONSTITUTION:An oxide film 2 is formed on a semiconductor substrate 1, a hole is bored in the oxide film 2, and impurity atoms are implanted in the whole surface of the semiconductor substrate 1 and an impurity diffusion layer 3 is formed onto the semiconductor substrate 1. Polycrystalline silicon 4 is deposited on the impurity diffusion layer 3, a thin silicon nitride film 5 is formed through nitriding, and a tungsten silicide 6 is deposited onto the silicon nitride film 5. Consequently, suction into the tungsten silicide 6 of impurities from the impurity diffusion layer 3 can be prevented by forming the silicon nitride film 5. Accordingly, increase of the contact resistance of the impurity diffusion layer 3 and the polycrystalline silicon 4 can be prevented, and the polycrystalline silicon 4 and the tungsten silicide 6 can be brought to an electrically connected state by a tunnel effect because of the thin silicon nitride film 5.

Cleaning of CVD reactor used in the production of polycrystalline silicon by impacting with carbon dioxide pellets

Abstract: The present invention is a process for the cleaning of the inner surfaces of a chemical vapor deposition reactor used in the production of polycrystalline silicon. The process comprises impacting the surfaces to be cleaned with solid carbon dioxide pellets. The carbon dioxide pellets dislodge silicon deposits from the surface of the reactor without damaging the surface of the reactor and without providing a source for contamination of polycrystalline silicon produced in the cleaned reactor. The present process is particularly useful for the cleaning of the inner surfaces of chemical vapor deposition reactors used in the production of semi-conductor grade silicon.