Showing papers on "Polycrystalline silicon published in 1992"

The extent of phase transformation in silicon hardness indentations

Abstract: The extent of phase transformation occurring in silicon during room-temperature indentation experiments has been examined by transmission electron microscopy of low-load microindents. The results show that the entire hardness impression arises from structural transformation and extrusion of a ductile high pressure phase. In particular, there is no dislocation activity or other mechanism of plastic deformation operating outside the clearly demarcated transformation zone. The observable impression consists of an amorphous transformation zone with an adjacent region of plastically extruded material and a layer of polycrystalline silicon at the near-surface transformation interface.

Method for producing a roughened surface capacitor

Abstract: A new method to produce a microminiturized capacitor having a roughened surface electrode is achieved. The method involves depositing a first polycrystalline or amorphous silicon layer over a suitable insulating base. The silicon layer is either in situ heavily, uniformly doped or deposited undoped and thereafter heavily doped by ion implantation followed by heating. The structure is annealed at above about 875° C. to render any amorphous silicon polycrystalline and to adjust the crystal grain size of the layer. The polysilicon surface is no subjected to a solution of phosphoric acid at a temperature of above about 140° C. to partially etch the surface and cause the uniformly roughened surface. A capacitor dielectric layer is deposited thereover. The capacitor structure is completed by depositing a second thin polycrystalline silicon layer over the capacitor dielectric layer.

Semiconductor substrate having a gettering layer

Abstract: A silicon wafer having a low concentration of oxygen and a silicon wafer having a high concentration of oxygen are joined and polished to prescribed thicknesses to form a semiconductor substrate according to the present invention. A region formed of the wafer having a low concentration of oxygen is used as a region where an element is formed, and a region formed of the wafer having a high concentration of oxygen produces a gettering effect on metal impurities and defects. As a DZ layer having a low concentration of oxygen, a wafer manufactured by an MCZ method or a wafer manufactured by a CZ method is used after being heat-treated at high temperature to diffuse oxygen outward. In another example, a damage layer, a polycrystalline silicon layer, an amorphous silicon layer or the like is formed between a DZ layer and an IG layer.

Structure of As‐Deposited LPCVD Silicon Films at Low Deposition Temperatures and Pressures

Abstract: In this work we studied the effect of the deposition temperature, total pressure, source gas dilution, and deposition rate on the structure of the as‐deposited silicon films. Depositions were performed by low pressure chemical vapor deposition (LPCVD) in the temperature range of 530 to 600°C and in the pressure range of 2 to 300 mTorr. For a fixed deposition temperature a phase transition from polycrystalline to amorphous silicon was shown to occur when the deposition rate exceeded a critical value. The critical value for the deposition rate was found to depend only upon the deposition temperature and to decrease as the temperature was decreased. By controlling the rate, as‐deposited polycrystalline silicon was obtained by conventional LPCVD at temperatues as low as 530°C. A relationship between the deposition rate and the partial pressure of the source gas was established via a kinetic model for the decomposition of silane and used to provide a simple model for the dependence of the structure of the as‐deposited silicon films upon the deposition parameters. This model was subsequently used to provide guidelines for both the expected structure of the as‐deposited films and the grain size of the as‐deposited polycrystalline silicon films over an extensive range of deposition conditions.

In-Situ Chemically Cleaning Poly-Si Growth at Low Temperature

Abstract: We report a novel growth method of polysilicon thin films on glass substrates at a low temperature (450°C) by plasma chemical vapor deposition (PCVD) using SiH4/SiF4 mixture gases. In this method, the conventional low-cost glass substrates such as Corning 7059 may be used because of the low deposition temperature. Furthermore, the conventional vacuum chamber with its base pressure of ~1×10-4 Pa, which is usually thought to be inadequate for high-quality Si growth because of its many impurities, can be used since the growing surface of polysilicon is in-situ chemically cleaned by SiF4 plasma. The polysilicon films obtained on glass show strong (100) preferred orientation. A grain size as large as 250 nm is obtained in a film with 700 nm thickness. The field-effect mobility of 44 cm2/Vs has been achieved in a thin-film transistor (TFT) using this polysilicon film.

Piezoresistivity in vapor-deposited diamond films

Abstract: We report the observation of a very large piezoresistive effect in both polycrystalline and homoepitaxial chemical‐vapor‐deposited diamond films. The gauge factor for polycrystalline p‐type diamond at 500 microstrains was found to be only 6 at room ambient, but increased rapidly with temperature, exceeding that of polycrystalline silicon (30) at 35 °C, and that of single‐crystal Si (120) at 50 °C. For strain and current flow in the [100] direction, the gauge factor of a (100)‐oriented homoepitaxial diamond film was found to be at least 550 at room temperature. Although the origins and unexpected temperature dependence of piezoresistive effect in diamond are not yet understood, these findings may suggest diamond‐based sensors with performance significantly superior to that of their Si counterparts.

Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings

Abstract: The invention is a product and method for forming same comprising a storage contact capacitor of a dynamic random access memory (DRAM) device wherein at least two annular rings and a vertical fin of silicon are fabricated in a self-aligned opening parallel to and in contact with the contact area of the substrate. The rings and fin comprise the storage node of the capacitor, and the fin is substantially centered in the rings. The fin is fabricated by forming silicon in a channel remaining after alternating layers of silicon and oxide are deposited in the opening. The final deposition of oxide is subjected to a spacer etch thereby retaining the final oxide only on sidewalls of the channel. The final oxide then functions as a masking pattern for extending the channel by subjecting the alternating layers to subsequent etches. The silicon fin contacts all of the silicon rings thereby providing electrical communication between the fin and the rings. Once the fin is formed the oxide is exposed, and at least portions of the oxide are etched. A dielectric layer is deposited to overlie the fins and a cell polycrystalline silicon layer is deposited to overlie the dielectric and complete the capacitor fabrication.

Manufacture of semiconductor device

Abstract: PURPOSE:To facilitate selection and control within a range, in which ions are not implanted, by equalizing the width of a sidewall film and the film thickness of a coated film when a stepped section is generated in the coated film deposited by the stepped section of a gate electrode section, the coated film is etched in an anisotropic manner and the sidewall film is formed. CONSTITUTION:Boron ions are implanted using a gate electrode 5 as a mask, and a P region 13 is formed in a polycrystalline silicon film 3 and an oxide film 10 of specified thickness is deposited. An oxide film pattern 11 is formed at a place, where the estimated maximum misalignment (a) is taken into consideration, and the oxide film pattern 11 is etched in an anisotropic manner while employing a nitride film 9 as a stopper from the state, thus shaping a sidewall film 12. The nitride film 9 is removed through etching, boron ions are implanted for forming source-drain diffusion layers in a P diffusion layer region, thus forming a P diffusion layer. The quantity of the offset of a TFT can be formed at a constant value regardless of the misalignment of a photoresist and the accuracy of finishing, thus allowing the inhibition of the variation of characteristics, thus stable performance characteristics are achieved.

Method of fabricating a polycrystalline silicon film having a reduced resistivity

Abstract: Disclosed is a method of forming a polycrystalline silicon film on a silicon oxide film in which the polycrystalline silicon film includes crystal grains having a large size, typically 4 micrometers, thereby permitting the resistivity of the polycrystalline silicon film to effectively be reduced. An amorphous silicon film is deposited on the silicon oxide film by using a chemical vapor deposition in which the flow rate of impurity gas remains at zero during an initial deposition, after which the flow rate is gradually increased from zero to a predetermined value during a final deposition. Thus, the amorphous silicon film comprises double layers, or an impurity unmixed region abutting the silicon oxide film and an impurity mixed region. After that, by a heat treatment, the amorphous silicon film is crystallized to form a polycrystalline silicon film. Concurrently, the impurity diffusion is accomplished.

Single mask process for forming both n-type and p-type gates in a polycrystalline silicon layer during the formation of a semiconductor device

Abstract: Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type. The second conductivity type is chosen so as to have minimal counterdoping effect of the previously doped polycrystalline silicon. Wafer processing continues.

Field effect transistor

Abstract: PURPOSE:To suppress leak current of a field effect transistor, thereby reducing the power consumption when the transistor is off, by providing the field effect transistor with the function of excluding a crrier from the channel forming area when the field effect transistor is off. CONSTITUTION:Polycrystalline silicon film 9 is connected to a power supply. Since film 9 is electrically connected also to polycrystalline silicon film 11, the same voltage as that of the power supply is applied through film 11 to channel forming area 12. Accordingly, when a p-type MOS transistor 21 is off, to the area 12 a positive voltage is applied, holes in area 12 all flow into drain area 13, and, as a result, the drain area 13 becomes empty of holes, thereby being able to suppress leak current between the source area 14 and the drain area 13.

Hydrogen diffusion in polycrystalline silicon thin films

Abstract: Grain boundaries in undoped polycrystalline silicon (poly‐Si) thin films are shown to act as efficient hydrogen traps rather than as paths of enhanced diffusion. A comparison of hydrogen diffusion in poly‐Si and undoped single‐crystal silicon (c‐Si) demonstrates that the diffusion in poly‐Si is significantly suppressed compared to c‐Si. These results have significant implications for hydrogenation of poly‐Si thin‐film transistors.

Method for making silicon-germanium devices using germanium implantation

Abstract: Silicon-germanium devices including MOSFETs, photogates and photodiodes, are produced by implanting the Si or polycrystalline silicon substrate with Ge + , to realize active SiGe regions within Si which are substantially free from defects, at an appropriate point in the fabrication by conventional techniques.

In-situ measurement of a thin film deposited on a wafer

Abstract: A method and apparatus is used to determine the thickness of a layer deposited on a specimen. For example, the thickness of a layer of polycrystalline may be measured as it is deposited over silicon oxide on a silicon wafer. The intensity of radiation emission at the top of the silicon wafer is detected. The temperature of the silicon wafer is measured and the variation in the intensity of radiation emission due to variation of the temperature is subtracted from the intensity of radiation emission detected at the top of the silicon wafer. The resultant signal is used to calculate the thickness of the polycrystalline silicon layer.

Interconnected silicon film solar cell array

Abstract: A plurality of thin polycrystalline silicon solar cells formed on a ceramic substrate and which are electrically series connected to form a monolithically interconnected submodule. Adjacent solar cells are electrically separated by a vertical trench and electrically connected by interconnects located below the light receiving surface of each solar cell. The submodules are provided with external electrical contacts for electrically connecting into a photovoltaic module assembly.

Low-temperature (<or=550 degrees C) fabrication of poly-Si thin-film transistors

Abstract: High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550 degrees C. This process features the use of polycrystalline Si/sub 0.5/Ge/sub 0.5/ for the gate material and high-dose H/sup +/ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm/sup 2//V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600 degrees C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates. >

Local interconnect for integrated circuits

Abstract: Local interconnect is defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors.

A method for anodizing a polysilicon layer lower capacitor plate of a dram to increase capacitance

Abstract: A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased by more than 1,000 percent using a storage node plate having microstructures thus formed.

Method of fabricating an offset dual gate thin film field effect transistor

Abstract: A method of fabricating an offset dual gate thin film field offset transistor wherein a lower gate electrode is formed on an insulating substrate is provided. A dielectric layer deposited. A polycrystalline silicon layer deposited and patterned to overlie and extend beyond the edges of the lower gate. A dielectric layer deposited. A metal layer deposited. A photoresist layer deposited and patterned to define a upper gate electrode in the metal layer that overlies the lower gate electrode but extend beyond one edge. The exposed metal layer is removed to form the upper gate electrode. An impurity is ion implanted into the polycrystalline silicon layer to form source and drain regions, using the photoresist layer and metal layer as a mask.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

Abstract: A low-temperature poly-Si thin-film transistor (TFT), having inverted-staggered structure, has been developed successfully using excimer laser annealing and ion doping. This TFT is suitable for pixel transistors of large-area and high-resolution LCDs. The maximum process temperature of the TFT fabrication steps is less than 450°C, so the same glass substrate on which amorphous Si TFT arrays are formed can be used in this poly-Si TFT process. Furthermore, most of the procedures, equipment and thin-film materials used to fabricate amorphous Si TFTs are compatible with fabrication of the poly-Si TFTs. On the other hand, some investigation of the CMOS driver circuit has been done, and it has been found that the threshold voltage of these poly-Si TFTs can be controlled easily by lightly doping of B ion into the channel region using the ion doping system.

Time‐dependent positive charge generation in very thin silicon oxide dielectrics

Abstract: We have studied the rate at which positive charge is generated starting near the oxide‐silicon interface when electrons are injected from the gate through the very thin oxide layer in metal‐oxide‐(p)silicon tunnel diodes. By varying the oxide thickness, we find that the charging rate is not strongly controlled by the flux of tunneling electrons over a five order of magnitude range in current density. This implies that if the tunneling electrons do participate, then the charge generation in these oxides is at least a two‐step process. A comparison of charge generation in aluminum and polycrystalline silicon gate devices suggests that the process does not involve aluminum‐related defects. Measurements of the charging rate versus temperature, T, show that it is weakly dependent on T below 150–200 K and apparently thermally activated above this temperature range.

Capacitor and method of fabricating same

Abstract: A stacked capacitor having a fin structure, and a method of fabrication. A first electrode with a fin structure is formed on a semiconductor substrate and a second electrode is formed over the first electrode and spaced therefrom by a dielectric film. The first electrode comprises an electrically conductive material, different from polycrystalline silicon, and a polycrystalline silicon film containing an impurity and covering the electrically conductive material. Thereby, the film thickness of the storage electrode of the fin capacitor is reduced and the corrugation of the surface of a memory device by the capacitor structure is mitigated.

Manufacture of semiconductor device

Abstract: PURPOSE:To unnecessitate a stopper and prevent a fin from sagging, by covering a first polycrystalline silicon film and a silicon dioxide film with a second polycrystalline silicon film, forming a side wall and a hole, and forming, on the surface, a silicon nitride film and a third polycrystalline silicon film turning to a counter electrode CONSTITUTION:On an Si substrate, every three layers composed of a first poly Si film 2 and an SiO2 film 3 turning to a multilayer fin type storage electrode are alternately stacked; patterning is performed; the stacked part is covered with a second poly Si film 4; by anisotropic etching, a side wall composed of the second poly Si film 4 is formed on the peripheral part of the first poly Si film 2; a hole 5 is formed at the central part of the films 2 and the films 3 so as to expose the first layer of the first poly Si film 2; by using resist for forming the hole 5 as a mask, the SiO2 film 3 is etched and completely eliminated; an Si3N4 film 6 is thinly stuck so as to cover the first poly Si film 2 and the second poly Si film 4; a third poly Si film 7 turning to a counter electrode is formed on the Si3N4 film 6 surface, thereby completing a device

Method of manufacturing thin film transistor and active matrix assembly including same

Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of less than 2500 Å and active matrix assemblies including thin film transistors provide improved thin-type displays.

Manufacture of semiconductor device

Abstract: PURPOSE:To enable a semiconductor device to be improved in accuracy of diffusion depth and easily turned in electrical characteristics by a method wherein a MISFET of double drain structure is used at both the center and the periphery of the semiconductor device, where a MISFET large in diffusion depth is provided to the center, and a MISFET small in diffusion depth is provided to the periphery CONSTITUTION:A first semiconductor region 36 is formed on a semiconductor substrate 30, and a field oxide film 33 is formed Then, an insulating film 32 is formed, then a polycrystalline silicon film is formed through a CVD method, for instance, and doped with phosphorus for the formation of a conductive layer 31 In succession, a MISFET 2 forming region is covered with a mask so as to prevent the periphery of the region from deteriorating in electrostatic breakdown strength, and phosphorus ions are implanted into a region where a third semiconductor region 35 is to be formed Then, the mask 40 is removed, then a diffusion process of the implanted phosphorus is performed in an oven to form a third semiconductor region 35 Then, phosphorus ions are implanted into all the regions where Nch-MISFET is to be formed Next, a diffusion process of the implanted phosphorus is performed in an oven to form third semiconductor regions 35 and 37 Arsenic ions are successively implanted into the same regions Furthermore, a thermal diffusion process of the implanted arsenic is performed in an oven for the formation of a second semiconductor region 39

Method for fabrication of semiconductor device

Abstract: This invention is directed to prevent step breakage and short-circuit of wires resulting from steps of isolation trenches formed in an SOI substrate. An oxide film for a pad is formed on a main plane of an SOI layer formed on an insulating substrate and furthermore, a silicon nitride film and an SiO2 film are sequentially formed. Thereafter, isolation trenches reaching the insulating substrate are formed by RIE using the SiO2 film as the mask. An insulating film is then formed on the inner wall of the isolation grooves by thermal oxidation, and polycrystalline silicon is filled into the insolation trenches. This polycrystalline silicon is etched back while control is made so that the upper end of polycrystalline silicon inside the isolation trenches is above the upper end of the silicon nitride film, and the excessive polycrystalline silicon deposited on the substrate surface is removed. Next, polycrystalline silicon inside the isolation trenches and the silicon nitride film are used as an etching stopper to etch and remove the SiO2 film used as the mask at the time of the formation of the isolation trenches. Since this etching and removal of the SiO2 film used as the mask is carried out after polycrystalline silicon is filled into the isolation trenches, the oxide film for isolating the substrates inside the SOI substrate is not etched when the mask is removed. When the masking SiO2 film is etched and removed, polycrystalline silicon and the silicon nitride film inside the isolation trenches function as the etching stopper, and the oxide film for the pad as the lower layer and the insulating film formed on the inner wall of the trenches are prevented from being etched, and flatness in the trench portions is not lost.

The I‐V characteristics of polycrystalline silicon diodes and the energy distribution of traps in grain boundaries

Abstract: The current-voltage characteristics of p+pn+ structure polycrystalline silicon diodes and the energy distribution of traps in the grain boundaries are measured before and after plasma hydrogenation. Plasma hydrogenation increases the forward current and reduces the reverse current. The energy distribution of nonhydrogenated film has a peak around the midgap; this peak disappears after hydrogenation. The change in diode current produced by plasma hydrogenation can be explained by this difference in the energy distribution of the traps.

Comparison of Transmission Electron Microscope Cross Sections of Amorphous Regions in Ion Implanted Silicon with Point‐Defect Density Calculations

Abstract: The width of the amorphous zone in the near-surface region of (100) silicon and polycrystalline silicon formed during high-dose silicon, phosphorus, or arsenic implantation is measured by cross-sectional transmission electron microscopy Various technologically important examples were selected for this study Comparison with point-defect density calculations yields a critical point-defect density for the crystalline-to-amorphous transition of 11510 22 cm -3 for all implantations The width of the amorphous zone may be predicted for Si + , P + and As + ilmplants with an accuracy of less than 5 %