Showing papers on "Polycrystalline silicon published in 1993"

Semiconductors for Solar Cells

Abstract: Physical principles of photovoltaic energy conversion technology of solar cell devices fundamental material parameters structural and electrical properties of lattice defects single crystal and polycrystalline silicon single crystal and epitaxial compound semiconductors thin-film compound semiconductors amorphous thin-film semiconductors.

Low temperature crystallization and patterning of amorphous silicon films on electrically insulating substrates

Abstract: A fabrication process polycrystalline silicon thin film transistors commences with the deposition of an ultra-thin nucleating-site forming layer onto the surface of an insulating substrate (e.g., 7059 glass). Next, an amorphous silicon film is deposited thereover and the combined films are annealed at temperatures that do not exceed 600° C. By patterning the deposition of the nucleating site forming material on the glass substrate, the subsequently deposited amorphous film can be selectively crystallized only in areas in contact with the nucleating-site forming material.

Optical functions of chemical vapor deposited thin‐film silicon determined by spectroscopic ellipsometry

Abstract: The optical functions of several forms of thin‐film silicon (amorphous Si, fine‐grain polycrystalline Si, and large‐grain polycrystalline Si) grown on oxidized Si have been determined using 2‐channel spectroscopic polarization modulation ellipsometry from 240 to 840 nm (∼1.5–5.2 eV). It is shown that the standard technique for simulating the optical functions of polycrystalline silicon (an effective medium consisting of crystalline Si, amorphous Si, and voids) does not fit the ellipsometry data.

Polycrystalline silicon thin film transistors on Corning 7059 glass substrates using short time, low‐temperature processing

Abstract: A new fabrication process for polycrystalline silicon thin film transistors on 7059 glass substrates is reported. This unique fabrication process has the advantages of short processing time and low processing temperature (≤600 °C). The processing is based on the key step of using an ultrathin Pd layer, introduced to the surface of the glass prior to the deposition of an a‐Si:H film, to reduce the crystallization time and temperature. It is also based on using an electron cyclotron resonance hydrogen plasma to reduced the passivation time. The n‐channel TFTs produced by this new fabrication process have mobilities of 20 cm2/V s, and off‐currents of 0.5 pA/μm.

Hydrogen passivation of grain boundary defects in polycrystalline silicon thin films

Abstract: The dependence of defect passivation in undoped polycrystalline silicon on hydrogenation conditions (i.e., time and temperature) was examined. At long hydrogenation times the spin density NS saturates. The saturation value of NS depends strongly on the hydrogenation temperature. The lowest residual spin density was obtained at 350 °C. Model calculations of the time and temperature dependence of the defect passivation suggest that the amount of hydrogen necessary for defect passivation exceeds the density of grain boundary defects by a factor that is significantly larger than unity and which depends on the hydrogenation temperature.

Room‐temperature luminescence from Er‐implanted semi‐insulating polycrystalline silicon

Abstract: Semi‐insulating polycrystalline silicon films with oxygen concentrations in the range 4–27 at. % were deposited by low‐pressure chemical vapor deposition of SiH4 and N2O onto silicon substrates, annealed at 920 °C, and then implanted with 2×1015 500 keV Er ions/cm2. After annealing at temperatures in the range 300–900 °C, the samples show intense room‐temperature luminescence around 1.54 μm, characteristic of intra‐4f emission from Er3+, upon excitation using an Ar ion laser. The luminescence intensity increases with increasing oxygen concentration in the film. The luminescence is attributed to Er3+ ions in oxygen‐rich shells around Si nanograins, excited by a photocarrier‐mediated process.

A dry-release method based on polymer columns for microstructure fabrication

Abstract: A fabrication process that eliminates the adhesion of surface-micromachined suspended mechanical structures to the underlying substrate during a sacrificial-etch release is presented. The method is based on the construction of a periodic array of polymer columns or rubber feet that stiffen the structure during the sacrificial etch. Flat polycrystalline silicon plates measuring 3000*3000*1- mu m suspended 1 mu m above the substrate are easily fabricated by this method. This process has applications in the fabrication of micromachined plates used in devices such as accelerometers and pressure sensors. >

Method of manufacturing semiconductor device

Abstract: PURPOSE:To realize a two-layer polycrystalline silicon capacitor with high performance and also prevent a characteristic from deteriorating due to an invasion of phosphorus into an MOS region by a method wherein, after a non- doped polycrystalline silicon is formed on the surface of a lower electrode, it is heated to form an oxidized film on the surface of the non-doped polycrystalline silicon. CONSTITUTION:A polycrystalline silicon 4 in which phosphorus is doped is set at least as a lower electrode. After a non-doped polycrystalline silicon 9 is formed on the surface of the lower electrode 4, it is heated. Thus, an oxidized film 6 is formed on the surface of the non-doped polycrystalline silicon 9. The phosphorus of the phosphorus-doped polycrystalline silicon 4 at forming the oxidized film 6 is scattered into the non-doped polycrystalline silicon 9, so that it is not evaporated in the gaseous phase. Thus, dispersion of an MOS threshold voltage is removed to obtain the MOS with a constant characteristic.

Manufacture of semiconductor

Abstract: PURPOSE: To obtain a polycrystalline silicon semiconductor film which has an excellent electric characteristic by a method wherein a hydrogenated amorphous silicon film is formed at low temperatures and is heat-treated in a vacuum and then it is dehydrogenated to generate a dangling bond in the film and the excimer laser is cast on the film in a vacuum-unbroken state. CONSTITUTION: An SiO 2 film or silicon nitride film is formed as a base protective film 12 on a glass substrate 11. Nextly, an intrinsic hydrogenated amorphous silicon semiconductor layer 13 is formed in the thickness of 100nm by the plasma CVD method. At that time, by setting the film formation temperature low, the formed amorphous silicon film is allowed to have in it a good quantity of water and bonds of silicon are neutralized with hydrogen as much as possible. Nextly, a device separation patterning is conducted and the sample is heated in a vacuum at 450°C for one hour to be dehydrogenated completely and dangling bonds (unpaired bonds) are generated in high density in the film. With the vacuum state being maintained, the excimer laser is cast on the sample to crystallize it. COPYRIGHT: (C)1993,JPO&Japio

Method for manufacturing a liquid crystal display substrate

Abstract: An amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the amorphous silicon film is changed to a plurality of polycrystalline silicon regions which are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses each having the same dimensions as those of the island region onto the amorphous silicon film, using a laser beam irradiating section. Switching elements including the island regions as semiconductor regions are formed by etching and film-forming process to constitute a driving circuit section. The section is divided to gate driving circuit sections and source driving circuit sections for driving thin film transistors formed in a pixel region.

Method of forming polycrystalline silicon film in process of manufacturing LCD

Abstract: In a method of forming a polycrystalline silicon film in a process of manufacturing an LCD, a hydrogenated amorphous silicon film is formed on a glass substrate by plasam CVD throughout areas serving as the pixel portion and driver unit of the LCD. A laser beam is radiated on a selected region of the film on the area serving as the driver unit. The energy of the laser beam is set such that hydrogen in the film is discharged without crystallizing the film and damaging the film. The energy of the laser beam is gradually increased to gradually discharge hydrogen from the film. The energy of the laser beam is finally set such that the film is transformed into a polycrystalline silicon film. The amorphous silicon film can be poly-crystallized without damaging the film by the discharge of hydrogen.

Conducting filament of the programmed metal electrode amorphous silicon antifuse

Abstract: Antifuses in PROM and FPGA applications have used silicon and/or polycrystalline silicon electrodes. Metal electrode antifuses have the lowest resistance and lowest capacitance among programmable interconnect structures. The ViaLink, a metal electrode amorphous silicon antifuse, has been used as a programmable interconnect device for a FPGA. This paper describes for the first time, the composition, structure, electrical characteristics, and temperature dependence of the conducting filament in the programmed TiW electrode amorphous silicon antifuse. >

Method of manufacturing semiconductor devices including rounding of corner portions by etching

Abstract: A method for rounding the corners of trench formed on the silicon substrate with metal, metal silicide or polycrystalline silicon thin film or the step portions of lead layers is provided. The steps of rounding are performed by chemical dry etching using a gas mixture of fluorine and oxygen. The abundance ratio of oxygen is determined to be one or more with respect to the fluorine. This method contributes significantly to the prevention of leakage current and the enhancement of insulating effect in the case of forming trench capacitors or the like.

Improvement of n-Type Poly-Si Film Properties by Solid Phase Crystallization Method

Abstract: Polycrystalline silicon (poly-Si) thin films prepared by the solid phase crystallization (SPC) method were investigated for application as photovoltaic materials. To improve the properties of the poly-Si thin film, two methods were developed to control crystallization. One is the partial doping method, in which starting material of a-Si consists of a doped layer and an undoped layer. We have succeeded in controlling nuclei generation using partial doping, and high mobility of 196 cm2/Vs was obtained at a carrier concentration of 1×1018 cm-3. SPC temperature can also be decreased to 500°C. The other is adoption, for the first time, of a textured substrate which exerted effects on the enlargement of grain size in poly-Si thin films prepared by the SPC method. By combining the partial doping method with the textured substrate, an n-type poly-Si thin-film with the grain size of 6 µm was fabricated which showed the Hall mobility of 623 cm2/Vs (n: 3.0\times1015 cm-3). In a solar cell (thickness: 12 µm) applying this film, a conversion efficiency of 6.2% was obtained and a collection efficiency of 50% was achieved at a wavelength of 900 nm.

Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same

Abstract: Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.

Effect of pressure on the growth of crystallites of low‐pressure chemical‐vapor‐deposited polycrystalline silicon films and the effective electron mobility under high normal field in thin‐film transistors

Abstract: The morphology of polycrystalline films grown by low‐pressure chemical‐vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth‐velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross‐sectional and plane‐view TEM analysis. In polycrystalline silicon thin‐film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposi...

On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

Abstract: A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator. >

Electrocal, thermal, thermoelectric and related properties of magnesium silicide semiconductor prepared from rice husk

Abstract: Polycrystalline, 10μm size magnesium silicide was prepared by alloying 99.9% purity polycrystalline silicon obtained from rice husk ash and high-purity magnesium powder. The material in sintered pellet form was characterized for its structural, electrical, thermal, thermoelectric and other properties. A typical sintered pellet exhibited a room-temperature (30°C) thermoelectric power of 565 μV K−1 and an electrical resistivity of 35 Ω cm. On the other hand, the material was found to be thermally quite stable up to 650°C with a room-temperature thermal conductivity of 6.3×10−3cals−1cm−1K−1 (2.6 J s−1 m−1 K−1). These properties of the material indicate that the material can find potential applications as a thermoelectric generator and in other semiconductor devices. Furthermore, an indigenous technology for large-scale production of silanes (SiH4) can be developed using this Mg2Si which could be prepared in large quantities by a simple and low-cost process.

Determination of bulk states and interface states distributions in polycrystalline silicon thin‐film transistors

Abstract: The field‐effect conductance activation energy Ea as a function of the gate voltage Vg is investigated for polycrystalline silicon thin‐film transistors. An analytical expression for Ea is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental Ea vs Vg data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin‐film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

Method of producing a semiconductor device having two MIS transistor circuits

Abstract: After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.

Method of manufacturing semiconductor device provided with capacitor and resistor

Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.

Physical properties of semi-insulating polycrystalline silicon. I. Structure, electronic properties, and electrical conductivity

Abstract: Semi‐insulating polycrystalline silicon (SIPOS) are thin SiOx films (0≤x≤2), deposited by means of low pressure chemical vapor deposition on suitable substrates (silicon or sapphire). Although SIPOS has important applications in the semiconductor and solar cell technology, its physical properties which depend strongly on the oxygen content x, are not well known. In the present contribution, SIPOS as deposited at 660 °C in the range 0≤x≤1 is investigated by using different and complementary methods, namely nuclear reaction analysis, secondary ion mass spectrometry, X‐ray photoelectron spectroscopy, high‐resolution transmission electron microscopy, and electrical conductivity measurements. On the basis of these experiments it is found that SIPOS consists of a nanometer‐scale mixture containing Si, SiO2, and at least one suboxide (SiO1−Δ with Δ≊0.14). SIPOS with x≤0.034 is polycrystalline, while SIPOS with x≥0.4 is completely amorphous. In the range 0.034≤x≤0.4 there is a transition from crystalline Si grain...

Method of fabricating field effect transistor having polycrystalline silicon gate junction

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Polycrystalline silicon thin-film transistors with two-step annealing process

Abstract: Thin-film transistors (TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature furnace annealing and high-temperature rapid thermal annealing leads to a significant improvement in the material quality. The TFTs obtained with this two-step annealing material exhibit better measured characteristics than those obtained by using conventional furnace annealing. >

Columnar-grained polycrystalline solar cell and process of manufacture

Abstract: The invention relates to techniques for manufacturing columnar-grained polycrystalline sheets which have particular utility as substrates or wafers for solar cells. The sheet is made by applying granular silicon to a setter material which supports the granular material. The setter material and granular silicon are subjected to a thermal profile all of which promote columnar growth by melting the silicon from the top downwardly. The thermal profile sequentially creates a melt region at the top of the granular silicon and then a growth region where both liquid and a growing polycrystalline sheet layer coexist. An annealing region is created where the temperature of the grown polycrystalline silicon sheet layer is controllably reduced to effect stress relief.

Buried plate type DRAM

Abstract: A trench of a buried plate type DRAM has a bottom portion wider than an opening portion. A silicon oxide film is formed on an upper portion of the side wall of the trench. An N-type impurity diffusion region is formed around the bottom portion of the trench. Impurity diffusion regions of adjacent trenches are integrally connected with each other as one portion. A first polycrystalline silicon layer is formed on the impurity diffusion region in the trench and the silicon oxide film. The polycrystalline silicon layer is coated with a laminated film consisting of a silicon nitride film and a silicon oxide film. The trench is filled with a second polycrystalline silicon layer covering the laminated film. The impurity diffusion region serves as a plate diffusion region of a capacitor, the first polycrystalline silicon layer serves as a plate electrode, the laminated film serves as a capacitor insulating film, and the second polycrystalline silicon layer serves as a storage node electrode. The capacitor is formed in the trench.

Surface Treatment Effect on the Grain Size and Surface Roughness of as‐Deposited LPCVD Polysilicon Films

Abstract: In this work we report on the effect of the substrate treatment on the grain size and the surface roughness of as‐deposited polycrystalline silicon films obtained by low pressure chemical vapor deposition. Deposition of silicon films was performed at 570°C on oxidized silicon substrates which were subjected to different wet surface treatments. We found that the grain size of the as‐deposited polysilicon films was significantly enhanced for films deposited on freshly oxidized silicon wafers, which were loaded immediately for deposition. This was attributed to the impurity‐free surface of the substrate, resulting in a lower nuclei density and subsequently in the development of a larger grain size. The surface roughness of these films, however, was found to be significantly higher than that of films deposited on substrates subjected to a wet surface treatment prior to deposition. The roughness was found to correlate well with the mechanism which predominantly determines the growth of the stable nuclei. When direct impingement of atoms on the nuclei predominates, a wave‐like surface develops while when lateral growth dominates, a smooth surface develops. We found that a smooth surface can be achieved either by subjecting the substrate in a wet surface treatment prior to deposition, which effectively decreases the surface diffusion length of the silicon adatoms and thus increases the density of the initial stable nuclei, or by suitably decreasing the deposition rate at a given temperature in the case of untreated substrates.

Polycrystalline silicon solar cells with a mechanically formed texturization

Abstract: Polycrystalline (Wacker SILSO) silicon has been mechanically textured using a conventional dicing saw and beveled blades for V‐groove formation. The minimum optical reflectivity achievable is limited by the blade tip radius and surface roughness after damage etching. Solar cells were prepared using a conventional diffusion and screen printed metallization. Grooved cells without an additional antireflection coating (jsc=31.8 mA/cm2, Voc=536 mV, FF=69%, η=11.8%) showed a 20% increase in jsc and a 1.1% absolute efficiency improvement as compared to a nongrooved reference cell with an antireflexion coating (jsc=26.4 mA/cm2, Voc=547 mV, FF=74.1%, η=10.7%). In grooved cells the efficiency is found to be limited mainly by the fill factor due to a nonoptimized front grid design.

Semiconductor substrate having a silicon-on-insulator structure and method of fabricating the same

Abstract: The invention provides a silicon-on-insulator semiconductor substrate structure and a method of fabricating the same. The structure includes a base silicon substrate, a mono-crystalline silicon film formed on the base silicon substrate in a predetermined region, a poly-crystalline silicon film formed on the base silicon substrate in opposite region to the predetermined region, an insulator film formed on the polycrystalline silicon film, and a mono-crystalline silicon layer overlaying both the insulator film and the mono-crystalline silicon film so that the mono-crystalline silicon layer is electrically connected to the base silicon substrate through the mono-crystalline silicon film. The mono-crystalline silicon film permits not the mono-crystalline silicon layer only but also the base silicon substrate to serve as active regions.

Process for the preparation of polycrystalline silicon ingot

Abstract: This invention relates to a process for the preparation of polycrystalline silicon ingots by providing a first layer of coating on the inside walls of a mold with a slurry of silicon nitride powder in an organic binder dissolved in a solvent; charging the said coated mold with silicon pieces along with calcium chloride or/and calcium fluoride; heating the mold to a temperature in the range of 1420°-1500° C. so as to melt the silicon, by keeping the mold inside the furnace; bringing down the temperature of the mold to a temperature 5°-10° C. above the melting point of silicon; withdrawing the mold containing the melt downwardly and slowly from the hot zone of the furnace so that the solidification of the melt starts from the bottom of the mold and proceeds towards the top as the withdrawal continues till all the melt solidifies; cooling the mold to the room temperature under inert atmosphere and removing the polycrystalline silicon ingot from the mold.