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Showing papers on "Polycrystalline silicon published in 2008"


Journal ArticleDOI
TL;DR: In this paper, the authors reviewed the recent advances in chemical and metallurgical routes for photovoltaic (PV) silicon production, and showed that the impressive growth is mainly based on solar cells made from polycrystalline silicon.

374 citations


Journal ArticleDOI
TL;DR: In this article, a low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) fabrication process on polyimide (PI) layers is presented.
Abstract: In this work we show a new low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) fabrication process on polyimide (PI) layers. The PI is spun on Si-wafer used as rigid carrier, thus overcoming difficulties in handling flexible freestanding plastic substrates, eliminating the problem of plastic shrinkage with high temperature processing and allowing the use of standard semiconductor equipment. LTPS TFTs are fabricated according to a conventional non self-aligned process, with source/drain contacts formed by deposition of a highly doped Si-layer and patterned by a selective wet-etching. Laser annealing is performed providing simultaneous dopant activation and crystallization of the active layer. The maximum process temperature is kept below 350 °C. After LTPS TFTs fabrication, the PI layer is mechanically released from the rigid carrier, which can be re-used for a new fabrication process. The devices exhibit good electrical characteristics with field effect mobility up to 50 cm 2 /V s. Analysis of electrical stability and characteristics in presence of mechanical stress is also shown.

122 citations


Patent
20 Oct 2008
TL;DR: In this paper, a trap-rich layer, such as a polycrystalline Silicon layer over a semiconductor substrate, is used to substantially immobilize a surface conduction layer at the surface of the semiconductor substrategies at radio frequency (RF) frequencies.
Abstract: The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.

89 citations


Journal ArticleDOI
TL;DR: In this article, the authors demonstrate on-chip active photonic devices fabricated from deposited polycrystalline silicon, which can be used for monolithic three-dimensional integration of optical networks.
Abstract: We experimentally demonstrate on-chip active photonic devices fabricated from deposited polycrystalline silicon, which can be used for monolithic three-dimensional integration of optical networks. The demonstrated modulator is based on all-optical carrier injection in a micrometer-size resonator and has a modulation depth of 10dB and a temporal response of 135ps. Grain boundaries in the polycrystalline silicon (polysilicon) material result in faster electron-hole recombination, enabling a shortened carrier lifetime and a faster optical switching time compared to similar devices based on crystalline silicon.

84 citations


Journal ArticleDOI
TL;DR: In this article, the authors proposed a method to evaluate minority carrier lifetime through photovoltage measurements by photoassisted Kelvin probe force microscopy and applied it to characterize a polycrystalline silicon solar cell.
Abstract: We have proposed a method to evaluate minority carrier lifetime through photovoltage measurements by photoassisted Kelvin probe force microscopy and have applied it to characterize a polycrystalline silicon solar cell. The results indicate that the lifetime significantly decreases in the vicinity of a grain boundary of the polycrystalline material. The photovoltage distribution around the grain boundary is also discussed by considering a contribution of both the intrinsic surface potential and the lifetime.

68 citations


Journal ArticleDOI
TL;DR: In this paper, the mechanism of particle generation is investigated in order to prevent defects formed on wafers in the plasma etching of multi-layered films composed of tungsten silicide (WSi) and polycrystalline silicon (poly-Si).
Abstract: The mechanism of particle generation is investigated in order to prevent defects formed on wafers in the plasma etching of multi-layered films composed of tungsten silicide (WSi) and polycrystalline silicon (poly-Si). Particles are measured by an in situ monitoring system using laser light scattering during the etching process. The particles are composed of AlF3, which is presumably generated by reacting the coating material Al2O3 on the etching chamber wall with plasma containing fluorine atoms, F in the presence of H2O absorbed into the chamber parts and materials. We demonstrated successfully that dehydration of the chamber parts and materials by plasma discharge suppresses particle generation.

68 citations


Journal ArticleDOI
TL;DR: In this paper, the positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated and the stress-induced hump in the sub-threshold region is observed and is attributed to the edge transistor along the channel width direction.
Abstract: Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.

65 citations


Journal ArticleDOI
TL;DR: In this article, the leakage current in the top-gate nanocrystalline silicon (nc-Si:H) thin film transistors was examined at various temperatures in an attempt to deduce the underlying off-state conduction mechanisms.
Abstract: The leakage current in the top-gate nanocrystalline silicon (nc-Si:H) thin film transistors was examined at various temperatures in an attempt to deduce the underlying off-state conduction mechanisms. Under high gate bias, the leakage current can be attributed to the thermal emission of trapped carriers at the midgap grain boundary states at low drain bias, while the behavior is reminiscent of the Poole–Frenkel emission in the drain depletion region at high drain bias. In contrast, Ohmic conduction through the bulk nc-Si:H channel layer seems to be the dominant mechanism of the leakage current under low gate bias.

61 citations


Journal ArticleDOI
TL;DR: In this article, the authors measured the propagation loss of poly-Si waveguide and coupling loss with optical flat polarization-maintaining fiber (PMF) for the whole C-band (i.e., λ~1520-1565nm).
Abstract: In this communication, the sub-micron size polycrystalline silicon (poly-Si) single mode waveguides are fabricated and integrated with SiON waveguide coupler by deep UV lithography. The propagation loss of poly-Si waveguide and coupling loss with optical flat polarization-maintaining fiber (PMF) are measured. For whole C-band (i.e., λ~1520-1565nm), the propagation loss of TE mode is measured to ~6.45±0.3dB/cm. The coupling loss with optical flat PMF is ~3.4dB/facet for TE mode. To the best of our knowledge, the propagation loss is among the best reported results. This communication discusses the factors reducing the propagation loss, especially the effect of the refractive index contrast. Compared to the SiO2 cladding, poly-Si waveguide with SiON cladding exhibits lower propagation loss.

60 citations


Journal ArticleDOI
TL;DR: In this article, the effect of both surface morphology and wet-chemical pre-treatment on electronic surface and interface properties was investigated for mono- and polycrystalline silicon substrates with special surface structures.

56 citations


Journal ArticleDOI
TL;DR: In this paper, a 3D modelling is used to obtain the expression of excess minority carrier density in the base region of a polycrystalline silicon solar cell and the concept of the junction recombination velocity S f was used to quantify how excess carrier flow through the junction in actual operating conditions.
Abstract: A 3D modelling is used to obtain the expression of excess minority carrier density in base region of a polycrystalline silicon solar cell. The concept of the junction recombination velocity S f is used to quantify how excess carrier flow through the junction in actual operating conditions. The plot of the photocurrent density allowed study the influence of the grain boundary recombination velocity and grain size on both, the junction recombination velocity and on the back surface recombination velocity of an n + - p - p + solar cell. This study pointed out the importance of the losses at the back side of solar cell. It's also show that the junction recombination velocity is more important for small grain size with large values of grain boundary recombination velocity.

Journal ArticleDOI
TL;DR: In this paper, a sequence of micron-scale wear mechanisms is proposed involving: 1) a short adhesive wear regime (< 104 cycles), where the oxide is worn away and the first silicon debris particles form and 2) a regime dominated by abrasive wear, where silicon particles (50-100 nm) are created by fracture through the grains (~500 nm).
Abstract: Micron-scale static friction and wear coefficients, surface roughness, and resulting wear debris have been studied for sliding wear in polycrystalline silicon in ambient air at micro- Newton normal loads using on-chip sidewall test specimens, fabricated with the Sandia SUMMiT VTM process. With increasing number of wear cycles friction coefficients increased by a factor of two up to a steady-state regime, concomitant with a decay (after an initial sharp increase) in the wear coefficients and roughness. Wear coefficients were orders of magnitude smaller than reported macroscale values, suggesting that the wear resistance is higher at micrometer dimensions. Based on our observations, a sequence of micron-scale wear mechanisms is proposed involving: 1) a short adhesive wear regime (< 104 cycles), where the oxide is worn away and the first silicon debris particles form and 2) a regime dominated by abrasive wear, where silicon particles (50-100 nm) are created by fracture through the grains (~500 nm). These particles subsequently oxidize and agglomerate into larger debris clusters, while "ploughing" by this debris leads to abrasive grooves associated with local cracking events rather than plastic deformation.

Journal ArticleDOI
TL;DR: In this article, an analysis of the hump effect in polycrystalline silicon TFTs is presented, combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge.
Abstract: Transfer characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) often show a “hump” in subthreshold regime. This effect, also observed in silicon-on-insulator (SOI) transistors, can be attributed to the presence of an enhanced electrical field at edges of the channel, which is related to the specific shape of the edge and its surrounding oxide. In this paper we attempt an analysis of the hump effect in polysilicon TFTs combining electrical measurements and two dimensional numerical simulations, and considering several geometries of the channel edge. The transfer characteristics showing the hump effect are analyzed in terms of a parallel of the main (“bulk”) transistor with two parasitic transistors located at the channel edges. The main and parasitic transistors have different threshold voltages and subthreshold swings and the equivalent parallel circuit reproduces very well the experimental transfer characteristics. The effect on the hump of interface states and oxide fixed...

Patent
13 May 2008
TL;DR: In this paper, a polysilicon rod for FZ applications is described, which is obtained by deposition of high-purity silicon from a silicon-containing reaction gas, which has been thermally decomposed or reduced by hydrogen, on a filament rod.
Abstract: The invention relates to a polysilicon rod for FZ applications obtainable by deposition of high-purity silicon from a silicon-containing reaction gas, which has been thermally decomposed or reduced by hydrogen, on a filament rod. The polysilicon rod contains, surrounding the filament rod, an inner zone having but few needle crystals, small in size, an outer zone having a relatively small amount of larger needle crystals, and a smooth transition zone between the inner and outer zones. The polysilicon rods are obtained in high yield and can be refined in one pass in an FZ process.

Journal ArticleDOI
TL;DR: In this paper, the authors used polysilicon resonators to determine stress-lifetime fatigue behavior in several environments, and found that oxide layers are found to show up to four-fold thickening after cycling, which is not seen after monotonic loading or after cycling in vacuo.

Journal ArticleDOI
TL;DR: In this article, the authors show that polycrystalline silicon (polysilicon) microelectromechanical systems (MEMS) devices subjected to constant tensile stresses do not display delayed fracture in humid ambients unless they also contain thick (>45nm) surface oxide layers, which are then susceptible to moisture-assisted stress corrosion.

Patent
21 Nov 2008
TL;DR: In this article, a polycrystalline silicon manufacturing apparatus is provided, in which a plurality of gas supplying ports 6 A for ejecting raw gas upward in a reactor and gas exhausting ports 7 for exhausting exhaust gas after a reaction are provided on an inner bottom of the reactor.
Abstract: A polycrystalline silicon manufacturing apparatus efficiently produces high-quality polycrystalline silicon. There is provided a polycrystalline silicon manufacturing apparatus, in which a plurality of gas supplying ports 6 A for ejecting raw gas upward in a reactor 1 and gas exhausting ports 7 for exhausting exhaust gas after a reaction are provided on an inner bottom of the reactor 1 in which a plurality of silicon seed rods 4 are stood, the silicon seed rods 4 are heated and the polycrystalline silicon is deposited from the raw gas on the surfaces. The apparatus includes gas distributing tubes 9 that are respectively connected to the gas supplying ports 6 A and respectively supply the raw gas to the gas supplying ports 6 A, valves 21 that are provided on at least the gas distributing tubes connected to the gas supplying ports 6 A adjacent to a center of the reactor 1 and open or close conduit lines of the gas distributing tubes 9 , and a valve controlling device 22 that is connected to the valves 21 and controls the conduit lines to be closed for a predetermined time at an early stage of the reaction.

Journal ArticleDOI
TL;DR: In this paper, a thin-film polycrystalline-silicon (pc-Si) solar cell was made using aluminium-induced crystallization and thermal CVD on alumina substrates.

Journal ArticleDOI
TL;DR: In this article, the effect of temperature, silane partial pressure, gas velocity and the size of bed particles has been studied in a laboratory-scale fluidized-bed reactor.
Abstract: The fluidized-bed chemical vapor deposition (CVD) process for polycrystalline silicon production is considered to be the most attractive alternative to the conventional bell-jar process. In order to obtain stable operation, high space-time-yields and high purity of the product several obstacles have to be eliminated. Reaction conditions must be optimized to avoid the homogeneous decomposition of silane and minimize silicon dust formation. The effect of temperature, silane partial pressure, gas velocity and the size of bed particles has to be identified. These dependencies and the interaction between hydrodynamics and kinetics of homogeneous and heterogeneous CVD-reactions were studied in a laboratory-scale fluidized-bed reactor.

Journal ArticleDOI
TL;DR: In this article, a surface micromachined silicon tribometer is employed to track changes in the adhesion and friction properties during repetitive normal and sliding contacts, and evidence for tribological degradation commences immediately for parallel sliding contact motion, and is slightly delayed in the case of repetitive impact loading normal to the surface.
Abstract: Reported here is a study of the tribological degradation of the contact interface of a fluorocarbon monolayer-coated polycrystalline silicon microdevice. A surface micromachined silicon tribometer is employed to track changes in the adhesion and friction properties during repetitive normal and sliding contacts. Evidence for tribological degradation commences immediately for parallel sliding contact motion, and is slightly delayed in the case of repetitive impact loading normal to the surface. The observed changes in interfacial behavior indicate dramatic changes in the chemical (i.e., surface energy) and physical (i.e., roughness, real contact area, etc.) nature of the contacting surfaces. Results from microscale sliding and impact experiments are interpreted in the light of the primary physical and chemical degradation mechanisms of monolayer-coated silicon microdevices.

Journal ArticleDOI
TL;DR: In this article, the insertion of Cr thin films between glass substrates and amorphous Si (a-Si) films by catalytic chemical vapor deposition (Cat-CVD) significantly improves the adhesion of Si films to the glass substrate, resulting in uniform crystallization of a-Si in 20×20 mm2 area.
Abstract: We have succeeded in forming polycrystalline silicon (poly-Si) films with thicknesses of over 4 µm on soda lime glass by flash lamp annealing (FLA) of precursor amorphous Si (a-Si) films deposited by catalytic chemical vapor deposition (Cat-CVD). The insertion of Cr thin films between glass substrates and a-Si significantly improves the adhesion of Si films to the glass substrates, resulting in uniform crystallization of a-Si in 20×20 mm2 area. Several types of substrate, such as quartz substrates, are also used instead of soda lime glass to elucidate the effects of the properties of glass substrates on formation of the poly-Si films. a-Si films tend to be crystallized under lower irradiance than those on quartz glass substrates, which can be described by the lower thermal conductivity and the thermal diffusion length of soda lime glass. Raman spectra of the poly-Si films on soda lime glass show high crystallinity close to unity. The utilization of soda lime glass with poor thermal resistivity is of great importance for the cost-effective mass production of thin-film poly-Si solar cells.

Patent
22 Sep 2008
TL;DR: In this paper, a polycrystalline silicon rod with a cross-section having a surface ratio of between 50 - 99 % of silicon for electric conduction and a bending strength of between 0.1 to 80 N/mm2 was described.
Abstract: The invention relates to a polycrystalline silicon rod that is characterised in that it has a rod cross-section having a surface ratio of between 50 - 99 % of silicon for electric conduction and the rod has a bending strength of between 0.1 to 80 N/mm2.

Journal ArticleDOI
TL;DR: In this article, a field effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition is presented, which shows high power efficiency and long lifetime.
Abstract: We report on a field-effect light emitting device based on silicon nanocrystals in silicon oxide deposited by plasma-enhanced chemical vapor deposition. The device shows high power efficiency and long lifetime. The power efficiency is enhanced up to ∼0.1% by the presence of a silicon nitride control layer. The leakage current reduction induced by this nitride buffer effectively increases the power efficiency two orders of magnitude with regard to similarly processed devices with solely oxide. In addition, the nitride cools down the electrons that reach the polycrystalline silicon gate lowering the formation of defects, which significantly reduces the device degradation.

Patent
26 Nov 2008
TL;DR: In this paper, the authors proposed a method for manufacturing polycrystalline silicon with high quality by effectively preventing undesired shape such as giving an rough surface to silicon rods or an irregularity in diameter of the silicon rods.
Abstract: A method for manufacturing polycrystalline silicon with high quality by effectively preventing undesired shape such as giving an rough surface to silicon rods or an irregularity in diameter of the silicon rods. The method for manufacturing polycrystalline silicon includes: an initial stabilizing step of deposition wherein a velocity of ejecting the raw material gas from the gas ejection ports is gradually increased; the shaping step wherein first the ejection velocity is increased at a rate higher than that in the stabilizing step and then the ejection velocity is gradually increased at a rate lower than the previous increasing rate; and a growing step wherein, after the shaping step, the ejection velocity is made slower than that at the end of the shaping step until the end of the deposition.

Patent
07 Nov 2008
TL;DR: In this article, a negative electrode material for a rechargeable battery with a nonaqueous electrolyte was proposed, characterized by the presence of polycrystalline silicon particles as an active material.
Abstract: This invention provides a negative electrode material for a rechargeable battery with a nonaqueous electrolyte, characterized in that the negative electrode material contains polycrystalline silicon particles as an active material, the particle diameter of crystallites of the polycrystalline silicon is not less than 20 nm and not more than 100 nm in terms of a crystallite size determined by the Scherrer method from the full width at half maximum of a diffraction line attributable to Si (111) around 2θ=28.4° in an x-ray diffraction pattern analysis, and the true specific gravity of the silicon particles is 2.300 to 2.320.

Patent
04 Feb 2008
TL;DR: In this paper, the bridged-grain structure (BG) is used to separate the intrinsic or lightly doped channel into multiple regions, and a single gate covering the entire active channel including the doped lines is still used to control the current flow.
Abstract: A low temperature polycrystalline silicon device and techniques to manufacture thereof with excellent performance. Employing doped poly-Si lines which we called a bridged-grain structure (BG), the intrinsic or lightly doped channel is separated into multiple regions. A single gate covering the entire active channel including the doped lines is still used to control the current flow. Using this BG poly-Si as an active layer and making sure the TFT is designed so that the current flows perpendicularly to the parallel lines of grains, grain boundary effects can be reduced. Reliability, uniformity and the electrical performance of the BG poly-Si TFT are significantly improved compared with the conventional low temperature poly-Si TFT.

Journal ArticleDOI
TL;DR: In this article, the surface morphology of n + -type polysilicon films from two popular MEMS processes and its effect on fracture and fatigue properties was analyzed using atomic force microscopy and transmission electron microscopy.
Abstract: Surface properties can markedly affect the mechanical behavior of structural thin films used in microelectromechanical systems (MEMS) applications. This study highlights the striking difference in the sidewall surface morphology of n + -type polysilicon films from two popular MEMS processes and its effect on fracture and fatigue properties. The sidewall surface roughness was measured using atomic force microscopy, whereas silicon oxide thickness and grain size were measured using (energy-filtered) transmission electron microscopy. These measurements show that the oxide layers are not always thin native oxides, as often assumed; moreover, the roughness of the silicon/silicon oxide interface is significantly influenced by the oxidation mechanism. Thick silicon oxides (20 ± 5 nm) found in PolyMUMPs™ films are caused by galvanic corrosion from the presence of gold on the chip, whereas in SUMMiT V™ films a much thinner (3.5 ± 1.0 nm) native oxide was observed. The thicker oxide layers, in combination with differences in sidewall roughness (14 ± 5 nm for PolyMUMPs™ and 10 ± 2 nm for SUMMiT V™), can have a significant effect on the reliability of polysilicon structures subjecting to bending loads; this is shown by measurements of the fracture strength (3.8 ± 0.3 GPa for PolyMUMPs™ and 4.8 ± 0.2 GPa for SUMMiT V™) and differences in the stress-lifetime cyclic fatigue behavior.

Patent
10 Jan 2008
TL;DR: In this paper, a complementary metal-oxide semiconductor (CMOS) device and a method of fabricating the CMOS semiconductor device are described. But the method is not described.
Abstract: Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained.

Patent
17 Mar 2008
TL;DR: In this paper, a nonaqueous electrolyte secondary battery negative electrode material was obtained in which while maintaining a high battery capacity and a low volume expansion coefficient of silicon oxide, a problem of a low first-time charge-discharge efficiency was solved, and which was superior in cycle characteristics.
Abstract: PROBLEM TO BE SOLVED: To provide a nonaqueous electrolyte secondary battery negative electrode material in which a proportion of polycrystalline silicon powders in an active material does not exceed 50 wt.%, and in which binder of 1 to 20 wt.% is contained in the negative electrode material regarding the negative electrode material composed of silicon oxide powders and polycrystalline silicon powders as the active material. SOLUTION: The nonaqueous electrolyte secondary battery negative electrode is obtained in which while maintaining a high battery capacity and a low volume expansion coefficient of silicon oxide, a problem of a low first-time charge-discharge efficiency that is the most important problem to be solved of the silicon oxide is solved, and which is superior in cycle characteristics. Moreover, the nonaqueous electrolyte secondary battery negative electrode material containing the silicon oxide as the active material is superior in adhesiveness to a current collector and a high initial efficiency, by using polyimide resin as the binder, and the nonaqueous secondary battery superior in cycle characteristics by repetition and efficiency is obtained since volume changes at the time of charge/discharge are moderated. COPYRIGHT: (C)2010,JPO&INPIT

Journal ArticleDOI
TL;DR: In this article, a working metallization scheme and first currentvoltage and quantum efficiency results of 2 cm2 EVA solar cells were presented for planar solar cells, which achieved fill factors up to 64%, series resistance values in the range of 4-5 Ωcm2, short-circuit current densities of up to 15.6 mA/cm2 and efficiencies of 4.25%.
Abstract: Polycrystalline silicon thin-film solar cells on glass obtained by solid-phase crystallization (SPC) of PECVD-deposited a-Si precursor diodes are capable of producing large-area devices with respectable photovoltaic efficiency. This has not yet been shown for equivalent devices made from evaporated Si precursor diodes (“EVA” solar cells). We demonstrate that there are two main problems for the metallization of EVA solar cells: (i) shunting of the p-n junction when the air-side metal contact is deposited; (ii) formation of the glass-side contact with low contact resistance and without shunting. We present a working metallization scheme and first current-voltage and quantum efficiency results of 2 cm2 EVA solar cells. The best planar EVA solar cells produced so far achieved fill factors up to 64%, series resistance values in the range of 4-5 Ωcm2, short-circuit current densities of up to 15.6 mA/cm2, and efficiencies of up to 4.25%. Using numerical device simulation, a diffusion length of about 4 𝜇m is demonstrated for such devices. These promising results confirm that the device fabrication scheme presented in this paper is well suited for the metallization of EVA solar cells and that the electronic properties of evaporated SPC poly-Si materials are sufficient for PV applications.