Showing papers on "Polycrystalline silicon published in 2009"

Thin‐Film Transistors

Abstract: Thin-film transistors (TFTs) matured later than silicon integrated circuits, but in the past 15 years the technology has grown into a huge industry based on display applications, with amorphous and polycrystalline silicon as the incumbent technology. Recently, an intense search has developed for new materials and new fabrication techniques that can improve the performance, lower manufacturing cost, and enable new functionality. There are now many new options – organic semiconductor (OSCs), metal oxides, nanowires, printing technology as well as thin-film silicon materials with new properties. All of the new materials have something to offer but none is entirely without technical problems.

High-Density Through Silicon Vias for 3-D LSIs

Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

High-Density Through Silicon Vias for 3-D LSIs : Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing

Abstract: High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chem- ical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

Deposited silicon high-speed integrated electro-optic modulator.

Abstract: We demonstrate a micrometer-scale electro-optic modulator operating at 2.5 Gbps and 10 dB extinction ratio that is fabricated entirely from deposited silicon. The polycrystalline silicon material exhibits properties that simultaneously enable high quality factor optical resonators and sub-nanosecond electrical carrier injection. We use an embedded p+n-n+ diode to achieve optical modulation using the free carrier plasma dispersion effect. Active optical devices in a deposited microelectronic material can break the dependence on the traditional single layer silicon-on-insulator platform and help lead to monolithic large-scale integration of photonic networks on a microprocessor chip.

Design and optimization of an ultra thin flexible capacitive humidity sensor

Abstract: In this paper we present the design and fabrication of a humidity sensor on ultra thin (8 μm) flexible polyimide substrate. The ultra thin flexible substrate can be preserved also when a read-out electronic interface is integrated by using Polycrystalline Silicon Thin Film Transistors technology. The sensor device is a capacitor where a thin layer of [bis(benzo cyclobutene)] is used as a dielectric sensitive material between two metal electrodes. The electrode layout has been designed with the aid of numerical simulations in order to optimize the sensor performances. The fabricated sensor has shown sensitivity to relative humidity of 0.38%/RH% and a linearity of 0.996 in the range of 10–90 RH%. Furthermore, measurements regarding the sensor response time, different bending and bias voltage effects have been performed.

Integration of Microstrip Patch Antenna With Polycrystalline Silicon Solar Cell

Abstract: The implementation of a polycrystalline silicon solar cell as a microwave groundplane in a low-profile, reduced-footprint microstrip patch antenna design for autonomous communication applications is reported. The effects on the antenna/solar performances due to the integration, different electrical conductivities in the silicon layer and variation in incident light intensity are investigated. The antenna sensitivity to the orientation of the anisotropic solar cell geometry is discussed.

Polycrystalline silicon on glass for thin-film solar cells

Abstract: Although most solar cell modules to date have been based on crystalline or polycrystalline wafers, these may be too material intensive and hence always too expensive to reach the very low costs required for large-scale impact of photovoltaics on the energy scene. Polycrystalline silicon on glass (CSG) solar cell technology was developed to address this difficulty as well as perceived fundamental difficulties with other thin-film technologies. The aim was to combine the advantages of standard silicon wafer-based technology, namely ruggedness, durability, good electronic properties and environmental soundness with the advantages of thin-films, specifically low material use, large monolithic construction and a desirable glass superstrate configuration. The challenge has been to match the different preferred processing temperatures of silicon and glass and to obtain strong solar absorption in notoriously weakly-absorbing silicon of only 1–2 micron thickness. A rugged, durable silicon thin-film technology has been developed with amongst the lowest manufacturing cost of these contenders and confirmed efficiency for small pilot line modules already in the 10–11% energy conversion efficiency range, on the path to 12–13%.

Slot waveguides with polycrystalline silicon for electrical injection.

Abstract: We demonstrate horizontal slot waveguides using high-index layers of polycrystalline and single crystalline silicon separated by a 10 nm layer of silicon dioxide. We measure waveguide propagation loss of 7 dB/cm and a ring resonator intrinsic quality factor of 83,000. The electric field of the optical mode is strongly enhanced in the low-index oxide layer, which can be used to induce a strong modal gain when an active material is embedded in the slot. Both high-index layers are made of electrically conductive silicon which can efficiently transport charge to the slot region. The incorporation of conductive silicon materials with high-Q slot waveguide cavities is a key step for realizing electrical tunneling devices such as electrically pumped silicon-based light sources.

Microstructure and photovoltaic performance of polycrystalline silicon thin films on temperature-stable ZnO:Al layers

Abstract: Polycrystalline silicon (poly-Si) thin films have been prepared by electron-beam evaporation and thermal annealing for the development of thin-film solar cells on glass coated with ZnO:Al as a transparent, conductive layer. The poly-Si microstructure and photovoltaic performance were investigated as functions of the deposition temperature by Raman spectroscopy, scanning and transmission electron microscopies including defect analysis, x-ray diffraction, external quantum efficiency, and open circuit measurements. It is found that two temperature regimes can be distinguished: Poly-Si films fabricated by deposition at low temperatures (Tdep 400 °C) directly in crystalline phase reveal columnar, up to 300 nm big crystals with a strong ⟨110⟩ orientation and much better solar cell parameters. It ...

Nonvolatile memory device and method of manufacturing the same

Abstract: Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.

Intragrain defects in polycrystalline silicon layers grown by aluminum-induced crystallization and epitaxy for thin-film solar cells

Abstract: Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason fo...

Thermochemical and Kinetic Databases for the Solar Cell Silicon Materials

Abstract: The fabrication of solar cell grade silicon (SOG-Si) feedstock involves processes that require direct contact between solid and a fluid phase at near equilibrium conditions Knowledge of the phase diagram and thermochemical properties of the Si-based system is, hence, important for providing boundary conditions in the analysis of processes A self-consistent thermodynamic description of the Si-Ag-Al-As-Au-B-Bi-C-Ca-Co-Cr-Cu-Fe-Ga-Ge-In-Li-Mg-Mn-Mo-N-Na-Ni-O-P-Pb-S-Sb-Sn-Te-Ti-V-W-Zn-Zr system has recently been developed by SINTEF Materials and Chemistry The assessed database has been designed for use within the composition space associated with the SoG-Si materials An assessed kinetic database covers the same system as in the thermochemical database The impurity diffusivities of Ag, Al, As, Au, B, Bi, C, Co, Cu, Fe, Ga, Ge, In, Li, Mg, Mn, N, Na, Ni, O, P, Sb, Te, Ti, Zn and the self diffusivity of Si in both solid and liquid silicon have extensively been investigated The databases can be regarded as the state-of-art equilibrium relations in the Si-based multicomponent system The thermochemical database has further been extended to simulate the surface tensions of liquid Si-based melts Many surface-related properties, eg, temperature and composition gradients, surface excess quantity, and even the driving force due to the surface segregation are possible to obtain directly from the database By coupling the Langmuir-McLean segregation model, the grain boundary segregations of the nondoping elements in polycrystalline silicon are also possible to estimate from the assessed thermochemical properties

Propagation losses in undoped and n-doped polycrystalline silicon wire waveguides

Abstract: Polycrystalline silicon (polySi) wire waveguides with width ranging from 200 to 500 nm are fabricated by solid-phase crystallization (SPC) of deposited amorphous silicon (a-Si) on SiO2 at a maximum temperature of 1000°C. The propagation loss at 1550 nm decreases from 13.0 to 9.8 dB/cm with the waveguide width shrinking from 500 to 300 nm while the 200-nm-wide waveguides exhibit quite large loss (>70 dB/cm) mainly due to the relatively rough sidewall of waveguides induced by the polySi dry etch. By modifying the process sequence, i.e., first patterning the a-Si layer into waveguides by dry etch and then SPC, the sidewall roughness is significantly improved but the polySi crystallinity is degraded, leading to 13.9 dB/cm loss in the 200-nm-wide waveguides while larger losses in the wider waveguides. Phosphorus implantation causes an additional loss in the polySi waveguides. The doping-induced optical loss increases relatively slowly with the phosphorus concentration increasing up to 1 × 1018 cm−3, whereas the 5 × 1018 cm−3 doped waveguides exhibit large loss due to the dominant free carrier absorption. For all undoped polySi waveguides, further 1–2 dB/cm loss reduction is obtained by a standard forming gas (10%H2 + 90%N2) annealing owing to the hydrogen passivation of Si dangling bonds present in polySi waveguides, achieving the lowest loss of 7.9 dB/cm in the 300-nm-wide polySi waveguides. However, for the phosphorus doped polySi waveguides, the propagation loss is slightly increased by the forming gas annealing.

Shunting Problems Due to Sub-Micron Pinholes in Evaporated Solid-Phase Crystallised Poly-Si Thin-Film Solar Cells on Glass

Abstract: Recent progress in the metallisation of poly-silicon thin-film solar cells on glass, created by solid phase crystallisation (SPC) of evaporated amorphous silicon (EVA), revealed that shunting through sub-micron holes (density 100–200 mm−2) in the films causes severe shunting problems when the air-side metal contact is deposited onto these diodes, by creating effective shunting paths between the two highly doped layers of EVA cells. We present evidence of these pinholes by optical transmission and focussed ion beam (FIB) microscopic images and confirm the point-like pinhole shunts using lock-in thermographic images. The latter revealed that the Al rear electrode induces strong ohmic shunts below the grid lines and a high density of weak non-linear shunts away from the grid lines. Two distinctly different approaches are shown to reduce the shunting problem to a negligible level: (i) to contact only a small fraction of the rear Si surface via a point contacting scheme, whereby the metal layer needs to be thin (<1 µm) and the fractional area coverage small (<5%), and (ii) to deposit line contacts in a bifacial interdigitated scheme, whereby a thick layer of metal is deposited followed by a wet-chemical etching step that effectively reduces shunting by preferentially etching away the shunting paths. Test devices with an area of 1 cm2 achieve pseudo fill factors (pFF) of above 75% and diode ideality factors of below 1·3, demonstrating that the proposed methods are well suited for the metallisation of the rear surface of EVA solar cells. Copyright © 2008 John Wiley & Sons, Ltd.

Rare-earth-containing glass material and substrate and device comprising such substrate

Abstract: A rare-earth-containing glass material having a composition, expressed in mole percentages on and oxide basis, comprising: SiO2: 66-75 Al2O3: 11-17 B2O3: 0-4 MgO: 1-6.5 CaO: 2-7 SrO: 0-4 BaO: 0-4 Y2O3: 0-4 La2O3: 0-4 Y2O3+La2O3: 0.1-4. The inclusion of Y2O3 and/or La2O3 in the composition reduces the T2.3 of the glass thereby allowing higher annealing-point glasses to be produced. The glass is particularly useful for low-temperature polycrystalline silicon-based semiconductor devices.

Silver-induced layer exchange for the low-temperature preparation of intrinsic polycrystalline silicon films

Abstract: The preparation of large grained continuous polycrystalline silicon layers by metal-induced crystallization is reported. The macroscopic layer exchange of an amorphous silicon precursor layer in contact with a silver layer was observed for temperatures below the softening point of glass. This process is quite similar to the well-known aluminum-induced layer exchange. However, due to the use of silver as a catalyst, the recrystallized layers are electrically intrinsic rather than highly doped with Al acceptors. The resulting polycrystalline silicon layers show a good crystalline quality as deduced from Raman scattering, x-ray diffraction, and UV-reflectance measurements.

Semiconductor memory integrated circuit and its manufacturing method

Abstract: A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film ( 21 a ) in the cell array region, gate oxide film ( 21 b ) for a high-voltage circuit and gate oxide film ( 21 c ) for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film ( 22 ). After that, device isolation grooves ( 13 ) are formed and buried with a device isolation insulating film ( 14 ). The first-layer polycrystalline silicon film ( 24 ) is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film ( 24 ) is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film ( 22 ) and the second-layer polycrystalline silicon film ( 24 ). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film ( 22 ), second-layer polycrystalline silicon film ( 24 ) and third-layer polycrystalline silicon film 28 , and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.

Influence of Hydrogen Plasma on the Defect Passivation of Polycrystalline Si Thin Film Solar Cells

Abstract: Hydrogen passivation (HP) of polycrystalline silicon (poly-Si) thin film solar cells was performed in a parallel plate radio-frequency (rf) plasma setup. The influence of hydrogen pressure p and electrode gap d on breakdown voltage Vbrk is presented showing that the minimum in Vbrk shifts with higher pressures towards higher p · d values. Cell test structures provided by CSG Solar AG were used to examine the influence of p and d on the open circuit voltage VOC. The highest VOC's were achieved for p · d values that correspond to a minimum in Vbrk. HP strongly improved the VOC. After the hydrogen plasma treatment the VOC improved significantly by a factor of 2 and amounted to 450 mV. Optimized parameters were then applied to different poly-Si solar cells prepared by electron beam evaporation.

Crystal growth of Si for solar cells

Abstract: Feedstock.- Czochralski Silicon Crystal Growth for Photovoltaic Applications.- Floating Zone Crystal Growth.- Crystallization of Silicon by a Directional Solidification Method.- Mechanism of Dendrite Crystal Growth.- Fundamental Understanding of Subgrain Boundaries.- New Crystalline Si Ribbon Materials for Photovoltaics.- Crystal Growth of Spherical Si.- Liquid Phase Epitaxy.- Vapor Phase Epitaxy.- Thin-Film Poly-Si Formed by Flash Lamp Annealing.- Polycrystalline Silicon Thin-Films Formed by the Aluminum-Induced Layer Exchange (ALILE) Process.- Thermochemical and Kinetic Databases for the Solar Cell Silicon Materials.

A two junction, four terminal photovoltaic device for enhanced light to electric power conversion using a low-cost dichroic mirror

Abstract: A low-cost dichroic mirror can be used successfully for solar spectrum splitting to enhance solar to electrical energy conversion. The mirror is optimized for use with a polycrystalline silicon photovoltaic cell pc-Si. With the dichroic mirror simultaneous excitation of a medium-efficient 11.1% commercial pc-Si and a custommade high band gap GaInP cell 12.3%, yields 16.8% efficiency, with both cells operating at maximum power. Our results clearly show that what is missing for this simple low-cost enhancement of Si solar cell efficiency are low-cost high band gap cells. © 2009 American Institute of Physics. DOI: 10.1063/1.3081510

Methods for fabricating bulk FinFET devices having deep trench isolation

Abstract: Methods are provided for fabricating Bulk FinFET devices having deep trench isolation. One or more deep isolation trenches are formed in a bulk silicon wafer. Mandrel-forming material is deposited overlying the bulk silicon wafer and dielectric pad layer thereon and simultaneously into the trench(es) as filler material. Mandrels are formed, overetching thereof creating a recess at the trench upper end. A conformal sidewall spacer material from which sidewall spacers are fabricated is deposited overlying the mandrels and into the recess forming a spacer overlying the filler material in the trench(es). Mandrels are removed using the spacer as an etch stop. Fin structures are formed from the bulk silicon wafer using the sidewall spacers as an etch mask. The mandrel-forming material is amorphous and/or polycrystalline silicon.

Numerical and experimental analysis on green laser crystallization of amorphous silicon thin films

Abstract: The effect of laser fluence on the crystallization of amorphous silicon irradiated by a frequency-doubled Nd:YAG laser is studied both theoretically and experimentally. An effective numerical model is set up to predict the melting threshold and the optimized laser fluence for the crystallization of 200-nm-thick amorphous silicon. The variation of the temperature distribution with time and the melt depth is analyzed. Besides the model, the Raman spectra of thin films treated with different fluences are measured to confirm the phase transition and to determine the optimized fluence. The calculating results accord well with those obtained from the experimental data in this research.

Methods to recover and purify silicon particles from saw kerf

Abstract: The present disclosure generally relates to methods for recovering silicon from saw kerf, or an exhausted abrasive slurry, resulting from the cutting of a silicon ingot, such as a single crystal or polycrystalline silicon ingot. More particularly, the present disclosure relates to methods for isolating and purifying silicon from saw kerf or the exhausted slurry, such that the resulting silicon may be used as a raw material, such as a solar grade silicon raw material.

Semiconductor device, and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To provide: a semiconductor device including a thin film transistor capable of being manufactured with high yield and high precision; and a manufacturing method thereof, by forming an alignment mark for producing the semiconductor device with high yield, without increasing the number of processes for producing the semiconductor device. SOLUTION: This semiconductor device is a semiconductor device 1 in which a polycrystalline silicon semiconductor film 13 and an alignment mark 4 made of a silicon film 5 defined as a graphic at least by silicon phases 6a, 6p having surfaces different from each other are formed on a substrate 10. These different silicon phases 6a, 6p are a polycrystalline silicon phase 6p and an amorphous silicon phase 6a. Such different silicon phases 6a, 6p can be formed by a method including: forming a mask pattern A for forming a polycrystalline silicon semiconductor film 13 in a semiconductor element part 2; forming a mask pattern B for forming an alignment mark 4 in an alignment mark part 3; and implanting ions from above the mask patterns A, B to convert at least the surface of an exposed part of the polycrystalline silicon film which is not covered by the mask patterns A, B to an amorphous silicon phase. COPYRIGHT: (C)2009,JPO&INPIT

Simulation and fabrication of heterojunction silicon solar cells from numerical computer and hot-wire CVD

Abstract: In this paper, we will present a Pc1D numerical simulation for heterojunction (HJ) silicon solar cells, and discuss their possibilities and limitations By means of modeling and numerical computer simulation, the influence of emitter-layer/intrinsic-layer/crystalline-Si heterostructures with different thickness and crystallinity on the solar cell performance is investigated and compared with hot wire chemical vapor deposition (HWCVD) experimental results A new technique for characterization of n-type microcrystalline silicon (n-µc-Si)/intrinsic amorphous silicon (i-a-Si)/crystalline silicon (c-Si) heterojunction solar cells from Pc1D is developed Results of numerical modeling as well as experimental data obtained using HWCVD on µc-Si (n)/a-Si (i)/c-Si (p) heterojunction are presented This work improves the understanding of HJ solar cells to derive arguments for design optimization Some simulated parameters of solar cells were obtained: the best results for Jsc = 39·4 mA/cm2, Voc = 0·64 V, FF = 83%, and η = 21% have been achieved After optimizing the deposition parameters of the n-layer and the H2 pretreatment of solar cell, the single-side HJ solar cells with Jsc = 34·6 mA/cm2, Voc = 0·615 V, FF = 71%, and an efficiency of 15·2% have been achieved The double-side HJ solar cell with Jsc = 34·8 mA/cm2, Voc = 0·645 V, FF = 73%, and an efficiency of 16·4% has been fabricated Copyright © 2009 John Wiley & Sons, Ltd

Semiconductor device, and manufacturing method thereof

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves reduced electric current leakage and parasitic resistance to achieve stable current gain. SOLUTION: A first polycrystalline semiconductor layer 120 i grown beneath a p-type polycrystalline silicon film 106 exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film 106 and a silicon nitride film 108, while growing the first semiconductor layer 110 on a n-type collector layer 102, and then the first polycrystalline semiconductor layer 120 is selectively removed. Further, second polycrystalline semiconductor layers 122 and 124 and third polycrystalline semiconductor layer 126 are selectively grown on the portion of the p-type polycrystalline semiconductor film 106 exposed in the lower surface of the visor section without contacting the silicon nitride film 108, while the second semiconductor layers 112 and 114 and the third semiconductor layer 116 are grown, so that the third semiconductor layer is in contact with the third polycrystalline semiconductor layer. COPYRIGHT: (C)2009,JPO&INPIT

Crystallization kinetics in electron-beam evaporated amorphous silicon on ZnO:Al-coated glass for thin film solar cells

Abstract: To systematically study the crystallization process of electron-beam evaporated amorphous silicon on ZnO:Al-coated glass for polycrystalline silicon thin film solar cells, transmission electron microscopy and optical microscopy were employed. A time and temperature dependent analysis allowed the individual investigation of the growth and nucleation processes. The growth velocities of Si-crystals on ZnO:Al and SiN-coated glass were found to be identical within the investigated temperature regime of 500–600 °C. However, with a high steady state nucleation rate and a low activation energy, the nucleation process of Si on ZnO:Al-coated glass has shown to differ significantly from nucleation on glass.