Showing papers on "Polycrystalline silicon published in 2010"

Effective light trapping in polycrystalline silicon thin-film solar cells by means of rear localized surface plasmons

Abstract: Significant photocurrent enhancement has been achieved for evaporated solid-phase-crystallized polycrystalline silicon thin-film solar cells on glass, due to light trapping provided by Ag nanoparticles located on the rear silicon surface of the cells. This configuration takes advantage of the high scattering cross-section and coupling efficiency of rear-located particles formed directly on the optically dense silicon layer. We report short-circuit current enhancement of 29% due to Ag nanoparticles, increasing to 38% when combined with a detached back surface reflector. Compared to conventional light trapping schemes for these cells, this method achieves 1/3 higher short-circuit current.

Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same

Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer

Characterization of polycrystalline silicon wafers for solar cells sliced with novel fixed-abrasive wire

Abstract: For slicing crystalline silicon ingots, we have developed a novel fixed-abrasive wire where diamond grit is fixed onto a bare wire by resin bonding. The properties of the wafers sliced using a multi-wire saw with the fixed-abrasive wire have been investigated. When compared with the wafers sliced with the loose-abrasive wire, the slicing speed is improved by approximately 2.5-fold and the thicknesses of saw-damage layers are reduced by more than a factor of two. Polycrystalline silicon solar cells have been fabricated for the first time utilizing the wafers sliced with the fixed-abrasive wire, and the cells with the saw-damage etching depth of 7 µm have shown photovoltaic properties comparable to those prepared using the wafers sliced with the loose-abrasive wire and subsequently etched to remove the damage layers up to 15 µm. It has been clarified that wafer slicing using the fixed-abrasive wire is promising as a next-generation slicing technique for fabrication of solar cells, particularly thin silicon cells where the wafer thicknesses approach or become less than 150 µm. Copyright © 2010 John Wiley & Sons, Ltd.

Low-loss amorphous silicon wire waveguide for integrated photonics: effect of fabrication process and the thermal stability

Abstract: Hydrogenated amorphous silicon (a-Si:H) wire waveguides were fabricated by plasma-enhanced chemical vapor deposition and anisotropic dry etching. With the optimized fabrication process, the propagation losses of as low as 3.2 ± 0.2 dB/cm for the TE mode and 2.3 ± 0.1 dB/cm for the TM mode were measured for the 200 nm (height) × 500 nm (width) wire waveguides at 1550 nm using the standard cutback method. The loss becomes larger at shorter wavelength (~4.4 dB/cm for TE and ~5.0 dB/cm for TM at 1520 nm) and smaller at longer wavelength (~1.9 dB/cm for TE and ~1.4 dB/cm for TM at 1620 nm). With the waveguide width shrinking from 500 nm to 300 nm, the TM mode loss keeps almost unchanged whereas the TE mode loss increases, indicating that the predominant loss contributor is the waveguide sidewall roughness, similar to the crystalline silicon waveguides. Although the a-Si:H and the upper cladding SiO2 were both deposited at 400°C, the propagation loss of the fabricated a-Si:H wire waveguides starts to increase upon furnace annealing under atmosphere at a temperature larger than 300°C: ~13-15 dB/cm after 400°C/30 min annealing and >70 dB/cm after 500°C/30 min annealing, which can be attributed to hydrogen out-diffusion. Even higher temperature (i.e., >600°C) annealing leads to the propagation loss approaching to the polycrystalline silicon counterparts (~40-50 dB/cm) due to onset of a-Si:H solid-phase crystallization.

47.2: 2.8-inch WQVGA Flexible AMOLED Using High Performance Low Temperature Polysilicon TFT on Plastic Substrates

Abstract: This paper reports a low-temperature polycrystalline silicon (LTPS) fabrication process on plastic substrate for a flexible AMOLED display. Characteristics of fabricated TFTs showed excellent performance with field effect mobility of 124.1 cm2/V-s, on/off ratio of >108, subthreshold slope of 0.30V/dec, and threshold voltage of −2.03V. Internal scan drive circuits, 1:3 demux, and compensation circuits were successfully integrated on the backplane of a 166ppi 2.8″ WQVGA flexible AMOLED panel.

Multiphysics Characterization of Transient Electrothermomechanical Responses of Through-Silicon Vias Applied With a Periodic Voltage Pulse

Abstract: Multiphysics characterization of transient electrothermomechanical responses of multilayered stacked through-silicon vias (TSVs) is performed with a modified hybrid time-domain finite-element method. Temperature dependence of most material parameters involved is considered, such as electrical and thermal conductivity, the thermal expansion coefficient, and Young's modulus. Transient temperature and thermal stress accumulation processes are studied in detail for various copper, polycrystalline silicon, and tungsten/polycrystalline silicon TSVs, with different periodic voltage pulses applied. It is shown that there are significant differences in the transient temperature and thermal stress responses among the three types of TSVs, which are all very sensitive to the variation of the surrounding silicon oxide isolation thickness. The algorithm and analysis will be useful in the design of stacked TSVs with high reliability.

Lifetime limiting recombination pathway in thin-film polycrystalline silicon on glass solar cells

Abstract: The minority carrier lifetimes of a variety of polycrystalline silicon solar cells are estimated from temperature-dependent quantum efficiency data. In most cases the lifetimes have Arrhenius temperature dependences with activation energies of 0.17–0.21 eV near room temperature. There is also a rough inverse relationship between lifetime and the base dopant concentration. Judging by this inverse law, the activation energies of the lifetimes, and the absence of plateau behavior in the lifetimes of the higher doped cells at low temperatures, it is inferred that the dominant recombination pathway involves the electronic transition between shallow states which are 0.05–0.07 eV below the conduction band and 0.06–0.09 eV above the valence band, respectively, consistent with the shallow bands in silicon dislocations. The modeled recombination behavior implies that deep levels do not significantly affect the lifetimes for most of the cells at and below room temperature.

EMRS Symp B Proceedings Formation of thin-film crystalline silicon on glass observed by in- situ XRD

Abstract: Thin-film poly-crystalline silicon (poly c-Si) on glass obtained by crystallization of an amorphous silicon (a-Si) film is a promising material for low cost, high efficiency solar cells. Our approach to obtain this material is to crystallize a-Si films on glass by solid phase crystallization (SPC). As the grain size of SPC poly c-Si films will be smaller than that of multi-crystalline wafers, lower solar cell efficiencies are expected for this technology. Despite the smaller grain size, a 2-micron-thick polycrystalline silicon solar cell with light trapping was shown to have a conversion efficiency of more than 10% [1]. Obtainable efficiencies up to 15% are expected for solar cells made using SPC of a-Si:H films. Expanding thermal plasma chemical vapor deposition (ETP-CVD) was used to prepare hydrogenated a-Si films; this technique is chosen because the deposition rates are much higher than with plasma enhanced CVD. A-Si:H films with different hydrogen contents were annealed using temperatures ranging from 500°C to 700°C. The evaluation of the films after annealing treatments revealed that the hydrogen content and bonding configuration did not influence the structural properties of the crystallized films significantly. The average crystallite size in the fully crystallized films was between 100 and 150 nm. Full crystallization of 1 micrometer thick films was achieved within 20 minutes for annealing at 625°C and 650°C. During annealing at 600°C crystallization is much slower, and no crystallization is observed at 500°C. The relation between the annealing temperature and the rate with which the films are fully crystallized is of great importance to develop a solar cell technology, to limit the thermal budget and processing time.

Advanced Micro-Polycrystalline Silicon Films Formed by Blue-Multi-Laser-Diode Annealing

Abstract: Semiconductor blue-multi-laser-diode annealing (BLDA) for amorphous Si film was performed to obtain a film containing uniform polycrystalline silicon (poly-Si) grains as a low temperature poly-Si (LTPS) process used for thin-film transistor (TFT). By adopting continuous wave (CW) mode at the 445 nm wavelength of the BLDA system, the light beam is efficiently absorbed into the thin amorphous silicon film of 50 nm thickness and can be crystallized stably. By adjusting simply the laser power below 6 W with controlled beam shape, the isotropic Si grains from uniform micro-grains to arbitral grain size of polycrystalline phase can be obtained with reproducible by fixing the scan speed at 500 mm/s. As a result of analysis using electron microscopy and atomic force microscopy (AFM), uniform distributed micro-poly-Si grains of smooth surface were observed at a power condition below 5 W and the preferred crystal orientation of (111) face was confirmed. As arbitral grain size can be obtained stably and reproducibly merely by controlling the laser power, BLDA is promising as a next-generation LTPS process for AM OLED panel including a system on glass (SoG).

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory. SOLUTION: A polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma CVD process so that the gate electrodes 7A, 7B are not in direct contact with the silicon nitride film 19. COPYRIGHT: (C)2011,JPO&INPIT

Random pn-junctions for physical cryptography

Abstract: In this paper, we report on high-rectification pn-diodes (rectification ratios up to 2×107) prepared by aluminum-induced crystallization on crystalline Si-wafers, which exhibit highly random I(V) characteristics. We argue that arrays of such diodes can be employed as physical uncloneable functions for cryptography. To resolve the structure of the active diode area, focused-ion beam imaging was used. The I(V) curves of the diodes reveal that both a smaller polycrystalline silicon film thickness and a smaller diode size lead to increasing randomness due to the increasing inhomogeneity of thinner films and due to more pronounced grain boundary effects for smaller diodes.

Thin film semiconductor device, display device using such thin film semiconductor device and manufacturing method thereof

Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.

Atomic-scale redistribution of dopants in polycrystalline silicon layers

Abstract: 80 nm thick polycrystalline silicon (poly-Si) layers implanted with As, P, and C were subjected to spike heating (1000 °C, 1.5 s) or laser anneal (1300 °C, 0.25 ms) and analyzed by atom probe tomography. A strong interfacial segregation of dopants to the grain boundaries (GBs) was revealed in the spike annealed samples. The heterogeneous precipitation of C to the GBs was observed, as well as the clustering of C in the interior of the grains. Theses clusters are also rich in As and P. Their shapes (loop, rod) strongly suggest that these clusters are the result of dopant segregation to extended defects. Nanometer size oxygen clusters were also observed. They originate from the recoil of oxygen atoms during the implantation process through the oxide layer. Laser annealed samples showed a lower segregation excess of dopants to GBs. Consequently, the dopant concentration inside grains was found larger compared to the spike annealed sample. The lower segregation rate at GB is explained by the larger temperature...

On the Controlling Mechanism of Preferential Orientation of Polycrystalline-Silicon Thin Films Grown by Aluminum-Induced Crystallization

Abstract: We investigated the controlling mechanism of preferential orientation in polycrystalline silicon (poly-Si) on glass substrate by Al-induced crystallization using an in situ monitoring system and electron backscattered diffraction (EBSD) measurements. Poly-Si film with (111)-preferential orientation was obtained by the layer exchange of the initial amorphous silicon (a-Si)/Al/glass into Al/poly-Si/glass. Cross-sectional EBSD revealed that Al crystal grains are much smaller than those of Si, and randomly oriented without any epitaxial relationship between (111)-oriented Si despite the fact that (111)-oriented Si is believed to originate from epitaxial growth on γ-Al2O3/Al(111). This suggests that another mechanism such as minimization of surface energy affects the formation of (111)-oriented poly-Si.

Physical and electrical characteristics of the high-k Ta2O5 "tantalum pentoxide… dielectric deposited on the polycrystalline silicon

Abstract: The high-k Ta2O5 films deposited on the polycrystalline silicon treated with different postrapid thermal annealing temperatures were formed as high-k interdielectrics. Physical and electrical characteristics of the Ta2O5 dielectrics were investigated with x-ray diffraction, x-ray photoelectron spectroscopy, atomic force microscopy, and electrical analysis. The annealing at 800 °C was found to be the optimal condition to reduce the defects and interface traps existed in the interface between the Ta2O5 dielectric and polysilicon to fabricate a well-crystallized film with higher breakdown field, lower leakage current and smaller charge trapping rate. This Ta2O5 dielectric shows promise for future generation of nonvolatile memory.

Degradation of photovoltaic modules under high voltage stress in the field

Abstract: The degradation in performance for eight photovoltaic (PV) modules stressed at high voltage (HV) is presented. Four types of modules—tandem-junction and triple-junction amorphous thin-film silicon, plus crystalline and polycrystalline silicon modules—were tested, with a pair of each biased at opposite polarities. They were deployed outdoors between 2001 and 2009 with their respective HV leakage currents through the module encapsulation continuously monitored with a data acquisition system, along with air temperature and relative humidity. For the first 5 years, all modules were biased continuously at fixed 600 VDC, day and night. In the last 2 years, the modules were step-bias stressed cyclically up and down in voltage between 10 and 600 VDC, in steps of tens to hundreds of volts. This allowed characterization of leakage current versus voltage under a large range of temperature and moisture conditions, facilitating determination of leakage paths. An analysis of the degradation is presented, along with integrated leakage charge. In HV operation: the bulk silicon modules degraded either insignificantly or at rates of 0.1%/yr higher than modules not biased at HV; for the thinfilm silicon modules, the added loss rates are insignificant for one type, or 0.2%/yr-0.6%/yr larger for the other type.

Polycrystalline silicon mass and process for producing polycrystalline silicon mass

Abstract: Provided is a clean high-purity polycrystalline silicon mass that has a low total content of chromium, iron, nickel, copper, and cobalt, which are heavy-metal impurities that cause a decrease in the quality of single-crystal silicon In the vicinity of each electrode-side end of a polycrystalline silicon rod obtained by the Siemens method, the total concentration of chromium, iron, nickel, copper, and cobalt is high Prior to the step of crushing the polycrystalline silicon rod (100), a cutting step is hence conducted in which the polycrystalline silicon parts of the polycrystalline silicon rod (100) taken out of the reactor which extend from the electrode-side ends to a distance of at least 70 mm therefrom are removed Thus, the polycrystalline silicon parts in which the total concentration of chromium, iron, nickel, copper, and cobalt in the bulk is 150 ppta or higher can be removed A polycrystalline silicon mass having a lower impurity concentration may be obtained by removing the polycrystalline silicon parts each extending to a distance of at least 155 mm

Characterization of Flowerlike Silicon Particles Obtained from Chemical Etching: Visible Fluorescence and Superhydrophobicity

Abstract: Flowerlike silicon particles are obtained by chemical etching of polycrystalline silicon polyhedrons using a mixture of hydrofluoric acid and nitric acid. The etched flowerlike particles show stable bright red photoluminescence under UV irradiation. The formation of pores with diameters of 3, 5.5, and 20 nm is revealed during etching. The etched particles exhibit superhydrophobic behavior with a contact angle of 158° because of the sharp tips of their “petals”. The source silicon polyhedrons are shown to possess radial grain boundaries. Preferential etching along the radial grain boundaries of the polyhedrons is thought to be the key reason for the formation of flowerlike porous silicon particles.

Manufacturing method of thin film transistor and transistor manufactured by method

Abstract: The invention discloses a manufacturing method of a thin film transistor and a transistor manufactured by the method, wherein the method is characterized by comprising the following steps: sequentially forming a surface covering layer, a polycrystalline silicon island active layer, a grid insulating layer, a grid electrode conducting layer and an auxiliary layer on a baseplate, photoetching the auxiliary layer to form an LDD forming layer, and forming a lightly doped drain electrode region, a heavily doped source electrode, a heavily doped drain electrode and a channel on the polycrystalline silicon island active layer by utilizing the action of the LDD forming layer and through only once doped ion implantation. The method of the invention only needs once ion implantation, simplifies the manufacturing working procedures and lowers the manufacturing cost; the thin film transistor which is manufactured by adopting the method and provided with a lightly doped drain electrode has the advantages of small electrode area and large numerical aperture.

Measurement of adhesion forces between polycrystalline silicon surfaces via a MEMS double-clamped beam test structure

Abstract: An electrostatically actuated double-clamped beam test structure has been designed and fabricated for the quantitative determination of adhesion forces between two contacting polycrystalline silicon (polysilicon) surfaces. The experimental measurements of the beam profile at varied bias and simulations based on finite element methods are combined to evaluate more accurately the adhesion forces experienced between polysilicon surfaces. In particular, the electrostatic force at pull-off is obtained by measuring the pull-off voltage and the beam profile through optical interferometric methods. The adhesion force is then determined from the mechanical restoring force obtained by finite element methods simulations and the calculated electrostatic force. The results show a weak scaling of the adhesion force with the apparent contact area, defined via microfabricated dimples.

Wire bonding as a cell interconnection technique for polycrystalline silicon thin‐film solar cells on glass

Abstract: The interconnection of solar cells is a critical part of photovoltaic module fabrication. In this paper, a high-yield, low-cost method for interconnecting polycrystalline silicon thin-film solar cells on glass is presented. The method consists of forming adjacent, electrically isolated groves across the cells using laser scribing, and then forming wire bonds over each laser scribe, resulting in series interconnection of the individual solar cells. Wire bonds are also used to connect the first and last solar cell in the string to external (tabbing) leads, forming a mini-module. A layer of white paint is then applied, which acts as both an encapsulation layer and an additional back surface reflector. Using this method, an 8·3% efficient mini-module has been fabricated. By exploiting recent developments in wire bonding technology, it appears that this process can be automated and will be capable of forming solar cell interconnections on large-area modules within relatively short processing times (∼10 min for a 1 m 2 module). Copyright © 2010 John Wiley & Sons, Ltd.

Polycrystalline silicon rod and device for producing same

Abstract: [Problems] To provide a polycrystalline silicon rod used for the recharging in the FZ method or the CZ method, the straight body portions thereof assuming an easily transferable shape and excelling in transferability. [Means for Solution] The polycrystalline silicon rod is obtained by depositing and growing silicon, by the chemical vapor-phase deposition method, on a silicon core member which includes a pair of silicon rods erected on the electrodes and a bridging portion connecting the upper ends of the silicon rods, wherein the straight body portions of the silicon rod erected on the electrodes have a diameter profile in the lengthwise direction thereof, and a minimum diameter is adjusted to be 60 to 95% of a maximum diameter.

Method for manufacturing semiconductor device

Abstract: The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; sequentially forming a gate oxide layer and a floating gate polycrystalline silicon layer on the semiconductor substrate; forming a large size of floating gate buffering oxide layer on the floating gate polycrystalline silicon layer in an active zone; segmenting the large size of floating gate buffering oxide layer into a plurality of small sizes of floating gate buffering oxide layers which are identical in size; executing chemical and mechanical polishing. According to the method, a wide window is provided for a following process through optimizing the pattern of the floating gate buffering oxide layer formed on the floating gate polycrystalline silicon layer in the large-area active zone after an FGBF photolithographic process, the problem that a recess is formed in the floating gate polycrystalline silicon layer in the large-area active zone after CMP is carried out on the floating gate polycrystalline silicon layer is solved, and the whole performance of an embedded flash memory and the qualified rate of the embedded flash memory are improved.