Showing papers on "Polycrystalline silicon published in 2013"

Back-End Deposited Silicon Photonics for Monolithic Integration on CMOS

Abstract: We present the vision of back-end deposited silicon photonics (BDSP) and review works that have been done in this field. Individual aspects of BDSP platform including excimer-laser-annealed polycrystalline silicon, low-loss plasma-enhanced chemical vapor deposition silicon nitride waveguide, modulator, detector, electrical interface, back-end CMOS compatibility, and benefits of the platform are discussed in detail.

Coherent phonon-grain boundary scattering in silicon inverse opals.

Abstract: We report measurements and modeling of thermal conductivity in periodic three-dimensional dielectric nanostructures, silicon inverse opals. Such structures represent a three-dimensional “phononic crystal” but affect heat flow instead of acoustics. Employing the Stober method, we fabricate high quality silica opal templates that on filling with amorphous silicon, etching and recrystallizing produce silicon inverse opals. The periodicities and shell thicknesses are in the range 420–900 and 18–38 nm, respectively. The thermal conductivity of inverse opal films are relatively low, ∼0.6–1.4 W/mK at 300 K and arise due to macroscopic bending of heat flow lines in the structure. The corresponding material thermal conductivity is in the range 5–12 W/mK and has an anomalous ∼T1.8 dependence at low temperatures, distinct from the typical ∼T3 behavior of bulk polycrystalline silicon. Using phonon scattering theory, we show such dependence arising from coherent phonon reflections in the intergrain region. This is con...

Development of a thermopile infrared sensor using stacked double polycrystalline silicon layers based on the CMOS process

Abstract: A stacked double-layer (SDL) thermopile-based infrared sensor, which comprised of 96 thermocouples on a suspended membrane, has been designed and fabricated with a CMOS-compatible process The thermoelectric properties were characterized, and responsivity (Rs) of 2028 V W−1 and detectivity (D*) of 285*108 cm Hz1/2 W−1 for a SDL thermopile were derived

Growth of vertical GaAs nanowires on an amorphous substrate via a fiber-textured Si platform.

Abstract: We demonstrate the vertical self-catalyzed molecular beam epitaxy (MBE) growth of GaAs nanowires on an amorphous SiO2 substrate by using a smooth [111] fiber-textured silicon thin film with very large grains, fabricated by aluminum-induced crystallization. This generic platform paves the way to the use of inexpensive substrates for the fabrication of dense ensembles of vertically standing nanowires (NWs) with promising perspectives for the integration of NWs in devices.

Polycrystalline silicon ingot, preparation method thereof, and polycrystalline silicon wafer

Abstract: Disclosed is a preparation method of a polycrystalline silicon ingot. The preparation method comprises: providing a silicon nucleation layer at the bottom of a crucible, and filling a silicon material above the silicon nucleation layer; heating the silicon material to melt same, adjusting the thermal field inside the crucible to make the melted silicon material to start crystallization on the basis of the silicon nucleation layer; and when the crystallization is finished, performing annealing and cooling to obtain a polycrystalline silicon ingot. By adopting the preparation method, a desirable initial nucleus can be obtained for a polycrystalline silicon ingot, so as to reduce dislocation multiplication during the growth of the polycrystalline silicon ingot. Further disclosed are a polycrystalline silicon ingot obtained through the preparation method and a polycrystalline silicon wafer made using the polycrystalline silicon ingot as a raw material.

Silicon carbide semiconductor device and method for producing the same

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Effects of crystallization mechanism on the electrical characteristics of green continuous-wave-laser-crystallized polycrystalline silicon thin film transistors

Abstract: Thin film transistors (TFTs) with amorphous silicon films crystallized via continuous-wave green laser at a wavelength of 532 nm exhibit very different electrical characteristics in various crystallization regions, corresponding to the Gaussian energy density distribution of the laser beam. In the center region subjected to the highest energy density, the full melting scheme led to the best crystallinity of the polycrystalline silicon film, resulting in the highest field-effect mobility of 500 cm2 V−1 s−1. In contrast, the edge region that resulted in solid phase crystallization exhibited the worst mobility of 48 cm2 V−1 s−1 for the polycrystalline silicon TFTs.

Method for forming inverted-pyramid porous surface nanometer texture on polycrystalline silicon and method for manufacturing short-wave reinforcing solar cell

Abstract: The invention discloses a method for forming an inverted-pyramid porous surface nanometer texture on polycrystalline silicon and a method for manufacturing a short-wave reinforcing solar cell. The method for forming the inverted-pyramid porous surface nanometer texture on the polycrystalline silicon and the method for manufacturing the short-wave reinforcing solar cell are suitable for the technical field of solar photovoltaic batteries. By means of a metal catalytic chemical corrosion method, a nanometer porous surface structure is formed on the polycrystalline silicon through HF, AgNO3, H2O2, HNO3 and other solutions, then partial samples are placed in a NaOH corrosive liquid with the concentration of 0.1-1% for surface modification of a nanometer inverted pyramid, a nanometer inverted pyramid silicon structure is formed, and the micro structure appearance of the nanometer inverted pyramid silicon structure is even and smooth, so that service life of a few effective charge carriers is greatly prolonged, and ultimately, in the nanometer texture surface structure, by means of changes of the thickness of a silicon nitride layer in the solar cell manufacturing process, a nanometer inverted pyramid silicon solar photovoltaic cell which is low in surface reflection rate and high in short wave spectrum response is prepared. The method for forming the inverted-pyramid porous surface nanometer texture on the polycrystalline silicon and the method for manufacturing the short-wave reinforcing solar cell are simple in process, convenient to operate, low in cost and suitable for industrial production.

Additive for acid texturing of diamond-wire-cutting polycrystalline silicon slices and application method thereof

Abstract: The invention provides an additive for acid texturing of diamond-wire-cutting polycrystalline silicon slices and an application method of the additive in the acid texturing process of diamond-wire-cutting polycrystalline silicon slices. The additive for acid texturing comprises the components of polyving akohol, polyethylene glycol and deionized water and is applied to the acid texturing process of diamond-wire-cutting polycrystalline silicon slices. Due to the fact that the additive is applied to the acid texturing process of diamond-wire-cutting polycrystalline silicon slices, reflectivity of the textured diamond-wire-cutting polycrystalline silicon slices is approximately 6% lower than that of the conventionally textured diamond-wire-cutting polycrystalline silicon slices. The additive for acid texturing is non-toxic and non-corrosive, preparation and application processes are simple, and practical application value is high.

Rapid recovery of polycrystalline silicon from kerf loss slurry using double-layer organic solvent sedimentation method

Abstract: The rapid development of photovoltaic (PV) industries has led to a shortage of silicon feedstock. However, more than 40% silicon goes into slurry wastes due to the kerf loss in the wafer slicing process. To effectively recycle polycrystalline silicon from the kerf loss slurry, an innovative double-layer organic solvent sedimentation process was presented in the paper. The sedimentation velocities of Si and SiC particles in some organic solvents were investigated. Considering the polarity, viscosity, and density of solvents, the chloroepoxy propane and carbon tetrachloride were selected to separate Si and SiC particles. It is found that Si and SiC particles in the slurry waste can be successfully separated by the double-layer organic solvent sedimentation method, which can greatly reduce the sedimentation time and improve the purity of obtained Si-rich and SiC-rich powders. The obtained Si-rich powders consist of 95.04% Si, and the cast Si ingot has 99.06% Si.

GaAs nanowire growth on polycrystalline silicon thin films using selective-area MOVPE

Abstract: The growth mechanism of GaAs nanowires (NWs) grown on polycrystalline silicon (poly-Si) thin films using selective-area metalorganic vapor-phase epitaxy was investigated. Wire structures were selectively grown in the mask openings on a poly-Si substrate. The appearance ratio of wire structures strongly depended on the growth conditions and deposition temperature of the poly-Si substrate. Evaluation of the grown shapes and growth characteristics revealed that GaAs NWs grown on a poly-Si substrate have the same growth mechanism as conventional GaAs NWs grown on a single-crystalline GaAs or Si substrate. Experiments showed that the wire structure yield can be improved by increasing the Si grain size and/or increasing the Si deposition temperature. The growth model proposed for understanding NW growth on poly-Si is based on the mask opening size, the Si grain size, and the growth conditions. The ability to control the growth mode is promising for the formation of NWs with complex structures on poly-Si thin layers.

Complementary metal oxide semiconductor (CMOS) circuit structure and manufacture method and display device thereof

Abstract: The invention discloses a complementary metal oxide semiconductor (CMOS) circuit structure and a manufacture method and a display device thereof. A P-channel metal oxide semiconductor (PMOS) area in the CMOS circuit structure is of a low temperature poly silicon (LTPS) thin film transistor (TFT) structure, namely a P type mingled polycrystalline silicon material is utilized to prepare a PMOS layer. An N-channel metal oxide semiconductor (NMOS) area is of an Oxide TFT structure, namely an oxide material is utilized to prepare an NMOS layer. The oxide material is utilized at the NMOS area to replace the existing polycrystalline silicon material to prepare the NMOS layer, three mingled processes of the NMOS area in the LTPS process are saved, manufacture flow of the CMOS circuit structure is simplified, and production cost is reduced. Further, the oxide material is adopted to manufacture the NMOS layer of the NMOS area, crystallization is only needed to be conducted on the PMOS layer in the PMOS area, service life of a laser tube is prolonged, and production cost is reduced.

Rare earth doped downshifting glass ceramics for photovoltaic applications

Abstract: The ability of fluorochlorozirconate (FCZ) glass ceramics containing hexagonal barium chloride nanocrystals doped with the rare earth elements, holmium and europium, to downshift ultraviolet light to wavelengths more usable by polycrystalline silicon photovoltaic cells was investigated. Six rare-earth-doped and one undoped FCZ glass samples were synthesized and subsequently heat treated to produce glass ceramics containing barium chloride nanocrystals in the hexagonal phase. The glasses were characterized by differential scanning calorimetry to determine crystallization temperatures for the heat treatment process. The resulting glass ceramics were characterized by X-ray diffraction, phosphorimetry, and spectrophotometry. All samples produce light centered at 470 nm when excited by ultraviolet radiation. The excitation spectra of FCZ glass ceramics containing hexagonal barium chloride nanocrystals doped or co-doped with divalent europium more closely matches the solar spectrum at the earth's surface than the excitation spectrum of an undoped sample. This feature of europium doped glass ceramics makes them suitable for the process of downshifting to improve the efficiency of polycrystalline silicon photovoltaic cells. The addition of holmium to the glass ceramics gives rise to additional emission at higher wavelengths and nearer to the band gap energy of polycrystalline silicon photovoltaic cells, reducing heating of the cells and thereby increasing cell efficiency. Additionally, the strong absorption by europium in the ultraviolet region of the spectrum may allow these glass ceramics to serve as a protective layer for ultraviolet sensitive materials.

Depletion-mode polysilicon optical modulators in a bulk complementary metal-oxide semiconductor process

Abstract: We demonstrate depletion-mode carrier-plasma optical modulators fabricated in a bulk complementary metal-oxide semiconductor (CMOS), DRAM-emulation process. To the best of our knowledge, these are the first depletion-mode modulators demonstrated in polycrystalline silicon and in bulk CMOS. The modulators are based on novel optical microcavities that utilize periodic spatial interference of two guided modes to create field nulls along waveguide sidewalls. At these nulls, electrical contacts can be placed while preserving a high optical Q. These cavities enable active devices in a process with no partial silicon etch and with lateral p–n junctions. We demonstrate two device variants at 5 Gbps data modulation rate near 1610 nm wavelength. One design shows 3.1 dB modulation depth with 1.5 dB insertion loss and an estimated 160 fJ/bit energy consumption, while a more compact device achieves 4.2 dB modulation depth with 4.0 dB insertion loss and 60 fJ/bit energy consumption. These modulators represent a significant breakthrough in enabling active photonics in bulk silicon CMOS—the platform of the majority of microelectronic logic and DRAM processes—and lay the groundwork for monolithically integrated CMOS-to-DRAM photonic links.

Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Abstract: We introduce a new structure for low-temperature polycrystalline silicon thin-film transistors (TFTs). This bridged-grain structure can reduce the threshold voltage and the subthreshold swing, increase the on-off ratio, and suppress leakage current and kink effect of TFTs significantly. This technique can be applied to all polycrystalline silicon TFTs, including those made by solid-phase crystallization, metal-induced crystallization, metal-induced lateral crystallization, and excimer laser annealing.

Nanophotonic light trapping in 3-dimensional thin-film silicon architectures

Abstract: Emerging low cost and large area periodic texturing methods promote the fabrication of complex absorber structures for thin film silicon solar cells. We present a comprehensive numerical analysis of a 2 μm square periodic polycrystalline silicon absorber architecture designed in our laboratories. Simulations are performed on the basis of a precise finite element reconstruction of the experimentally realized silicon structure. In contrast to many other publications, superstrate light trapping effects are included in our model. Excellent agreement to measured absorptance spectra is obtained. For the inclusion of the absorber into a standard single junction cell layout, we show that light trapping close to the Yablonovitch limit can be realized, but is usually strongly damped by parasitic absorption.

Material structures for front-end of the line integration of optical polarization splitters and rotators

Abstract: A polarization splitter and rotator of a wafer chip, an opto-electronic device and method of use is disclosed. The first waveguide of the wafer chip is configured to receive an optical signal from an optical device and propagate a transverse electric eigenstate of the received optical signal. The second waveguide is configured to receive a transverse magnetic eigenstate of the received optical signal from the first waveguide. The second waveguide includes a splitter end, a middle section and a rotator end, wherein the splitter end includes a layer of polycrystalline silicon, a layer of silicon oxide and a layer of silicon nitride, the rotated end includes a layer single crystal silicon, a layer silicon oxide and a layer of silicon nitride, and the middle section includes layers of single crystal silicon, silicon oxide polycrystalline silicon and silicon nitride.

Highly Selective Etching of SiO2 over Si3N4 and Si in Capacitively Coupled Plasma Employing C5HF7 Gas

Abstract: In a dual-frequency-excited parallel plate capacitively coupled plasma employing a heptafluoro-cyclo-pentene (C5HF7) gas with addition of O2 and dilution in Ar gas, highly selective etching of SiO2 at selectivities of 40 against Si3N4 and 57 against polycrystalline Si was realized. Gas phase fluorocarbon species containing H atoms such as CxHFy (x>2) played key roles in the selective deposition of thick hydrofluorocarbon films that covered the Si3N4 and polycrystalline silicon (poly-Si) surfaces and in the selective etching of SiO2 over the photoresist, SiN, and Si.

Highest Efficiency Plasmonic Polycrystalline Silicon Thin-Film Solar Cells by Optimization of Plasmonic Nanoparticle Fabrication

Abstract: Excitation of surface plasmons in metallic nanoparticles is a promising method for increasing the light absorption in solar cells and hence the cell photocurrent. Comprehensive optimization of a nanoparticle fabrication process for enhanced performance of polycrystalline silicon thin-film solar cells is presented. Three factors were studied: the Ag precursor film thickness, annealing temperature and time. The thickness of the precursor film was 10, 14 and 20 nm; annealing temperature was 190, 200, 230 and 260 °C; and annealing time was varied between 20 and 95 min. Performance enhancement due to light-scattering by nanoparticles was calculated by comparing absorption, short-circuit current density and energy conversion efficiency in solar cells with and without nanoparticles formed under different process conditions. Nanoparticles formed from 14-nm-thick Ag precursor film annealed at 230 °C for 53 min result in the highest absorption enhancement in the 700–1,100 nm wavelength range, in the highest enhancement of total short-circuit current density. The highest photocurrent enhancement was 33.5 %, which was achieved by the cell with the highest absorption enhancement in the 700–1,100 nm range. The plasmonic cell efficiency of 5.32 % was achieved without a back reflector and 5.95 % with the back reflector; which is the highest reported efficiency for plasmonic thin-film solar cells.

Thermal behavior of parasitic resistances of polycrystalline silicon solar cells

Abstract: In this work, we investigate the influence of temperature on the series and shunt resistances of polycrystalline silicon solar cells and then to determine the specific expressions of both parasitic resistances as function of temperature. We have exploited the current-voltage characteristics of polycrystalline silicon solar cell at different temperatures and under constant illumination (1000 W/m 2 ). The obtained results show that the series resistance,

Ultra-low reflectivity polycrystalline silicon surfaces formed by surface structure chemical transfer method

Abstract: A nanocrystalline Si layer can be formed by the surface structure chemical transfer (SSCT) method in which a platinum mesh is instantaneously contacted with polycrystalline Si wafers immersed in hydrogen peroxide plus hydrofluoric acid solutions The polycrystalline Si surface after the SSCT method possesses an ultra-low reflectivity The nanocrystalline Si layer possesses a 100–150 nm thickness, and gives a photoluminescence with a peak maximum at ∼670 nm, indicating band-gap widening The minority carrier lifetime of as-sliced Si wafers greatly increases after the SSCT method most probably due to the enlargement of the nanocrystalline Si band-gap