Showing papers on "Polycrystalline silicon published in 2014"

Ultra-high mobility transparent organic thin film transistors grown by an off-centre spin-coating method

Abstract: One of the advantages of organic over inorganic semiconductors is they can be grown from solution, but their electrical mobility is often poor. Yuan et al. report a technique for fabricating organic transistors with mobilities far beyond that of amorphous silicon and close to that of polycrystalline silicon.

Carrier-selective contacts for Si solar cells

Abstract: Carrier-selective contacts (i.e., minority carrier mirrors) are one of the last remaining obstacles to approaching the theoretical efficiency limit of silicon solar cells. In the 1980s, it was already demonstrated that n-type polysilicon and semi-insulating polycrystalline silicon emitters form carrier-selective emitters which enabled open-circuit voltages (Voc) of up to 720 mV. Albeit promising, to date a polysilicon emitter solar cell having a high fill factor (FF) has not been demonstrated yet. In this work, we report a polysilicon emitter related solar cell achieving both a high Voc = 694 mV and FF = 81%. The passivation mechanism of these so-called tunnel oxide passivated contacts will be outlined and the impact of TCO (transparent conductive oxide) deposition on the injection-dependent lifetime characteristic of the emitter as well as its implications on FF will be discussed. Finally, possible transport paths across the tunnel oxide barrier will be discussed and it will be shown that the passivating...

On-chip silicon optical phased array for two-dimensional beam steering.

Abstract: A 16-element optical phased array integrated on chip is presented for achieving two-dimensional (2D) optical beam steering. The device is fabricated on the silicon-on-insulator platform with a 250 nm silicon device layer. Steering is achieved via a combination of wavelength tuning and thermo-optic phase shifting with a switching power of Pπ=20 mW per channel. Using a silicon waveguide grating with a polycrystalline silicon overlay enables narrow far field beam widths while mitigating the precise etching needed for conventional shallow etch gratings. Using this system, 2D steering across a 20°×15° field of view is achieved with a sidelobe level better than 10 dB and with beam widths of 1.2°×0.5°.

Dopant etch selectivity control

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Progress in Laser-Crystallized Thin-Film Polycrystalline Silicon Solar Cells: Intermediate Layers, Light Trapping, and Metallization

Abstract: Diode laser crystallization of thin silicon films on the glass has been used to form polycrystalline silicon layers for solar cells. Properties of an intermediate layer stack of sputtered SiOx/SiNx/SiOx between the glass and the silicon have been improved by reactively sputtering the SiNx layer, which result in enhanced optical and electrical performance. Light trapping is further enhanced by texturing the rear surface of the silicon prior to metallization. An initial efficiency of 11.7% with VOC of 585 mV has been achieved using this technique, which are the highest values reported for poly-Si solar cells on glass substrates. Cells suffer a short term, recoverable degradation of VOC, and fill factor. The magnitude of the degradation is reduced via the repeated thermal treatment. A selective p+ metallization scheme has been developed which eliminates the degradation altogether.

Review of Microcrack Detection Techniques for Silicon Solar Cells

Abstract: Microcracks at the device level in bulk solar cells are the current subject of substantial research by the photovoltaic (PV) industry. This review paper addresses nondestructive testing techniques that are used to detect microfacial and subfacial cracks. In this paper, we mainly focused on mono- and polycrystalline silicon PV devices and the root causes of the cracks in solar cells are described. We have categorized these cracks based on size and location in the wafer. The impact of the microcracks on electrical and mechanical performance of silicon solar cells is reviewed. For the first time, we have used the multi-attribute decision-making method to evaluate the different inspection tools that are available on the market. The decision-making tool is based on the analytical hierarchy process and our approach enables the ranking of the inspection tools for PV production stages, which have conflicting objectives and multi-attribute constraints.

Transparent, High-Performance Thin-Film Transistors with an InGaZnO/Aligned-SnO2-Nanowire Composite and their Application in Photodetectors

Abstract: A high mobility of 109.0 cm(2) V(-1) s(-1) is obtained by thin-film transistors (TFTs) comprising a composite made by aligning SnO2 nanowires (NWs) in amorphous InGaZnO (a-IGZO) thin films. This composite TFT reaches an on-current density of 61.4 μA μm(-1) with a 10 μm channel length. Its performance surpasses that of single-crystalline InGaZnO and is comparable with that of polycrystalline silicon.

Nanoindentation of polysilicon and single crystal silicon: Molecular dynamics simulation and experimental validation

Abstract: This paper presents novel advances in the deformation behaviour of polycrystalline and single crystal silicon using molecular dynamics (MD) simulation and validation of the same via nanoindentation experiments. In order to unravel the mechanism of deformation, four simulations were performed: indentation of a polycrystalline silicon substrate with a (i) Berkovich pyramidal and a (ii) spherical (arc) indenter, and (iii and iv) indentation of a single crystal silicon substrate with these two indenters. The simulation results reveal that high pressure phase transformation (HPPT) in silicon (Si-I to Si-II phase transformation) occurred in all cases; however, its extent and the manner in which it occurred differed significantly between polycrystalline silicon and single crystal silicon, and was the main driver of differences in the nanoindentation deformation behaviour between these two types of silicon. Interestingly, in polycrystalline silicon, the HPPT was observed to occur more preferentially along the grain boundaries than across the grain boundaries. An automated dislocation extraction algorithm (DXA) revealed no dislocations in the deformation zone, suggesting that HPPT is the primary mechanism in inducing plasticity in silicon.

Transformational silicon electronics.

Abstract: In today’s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry’s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage ...

All-silicon spherical-Mie-resonator photodiode with spectral response in the infrared region

Abstract: Silicon is the material of choice for visible light photodetection and solar cell fabrication. However, due to the intrinsic band gap properties of silicon, most infrared photons are energetically useless. Here, we show the first example of a photodiode developed on a micrometre scale sphere made of polycrystalline silicon whose photocurrent shows the Mie modes of a classical spherical resonator. The long dwell time of resonating photons enhances the photocurrent response, extending it into the infrared region well beyond the absorption edge of bulk silicon. It opens the door for developing solar cells and photodetectors that may harvest infrared light more efficiently than silicon photovoltaic devices that are so far developed.

Direct integration of a supercapacitor into the backside of a silicon photovoltaic device

Abstract: We demonstrate a route to integrate active material for energy storage directly into a silicon photovoltaic (PV) device, and the synergistic operation of the PV and storage systems for load leveling. Porous silicon supercapacitors with 84% Coulombic efficiency are etched directly into the excess absorbing layer material in a commercially available polycrystalline silicon PV device and coupled with solid-state polymer electrolytes. Our work demonstrates the simple idea both that the PV device can charge the supercapacitor under an external load and that a constant current load can be maintained through periods of intermittent illumination, demonstrating the concept of an all-silicon integrated solar supercapacitor.

Crystal Growth and Evaluation of Silicon for VLSI and ULSI

Abstract: Preface About the Author Introduction Silicon: The Semiconductor Why Single Crystals Revolution in Integrated Circuit Fabrication Technology and the Art of Device Miniaturization Use of Silicon as a Semiconductor Silicon Devices for Boolean Applications Integration of Silicon Devices and the Art of Circuit Miniaturization MOS and CMOS Devices for Digital Applications LSI, VLSI, and ULSI Circuits and Applications Silicon for MEMS Applications Summary References Silicon: The Key Material for Integrated Circuit Fabrication Technology Introduction Preparation of Raw Silicon Material Metallurgical-Grade Silicon Purification of Metallurgical-Grade Silicon Ultra-High Pure Silicon for Electronics Application Polycrystalline Silicon Feed for Crystal Growth Summary References Importance of Single Crystals for Integrated Circuit Fabrication Introduction Crystal Structures Different Crystal Structures in Nature Cubic Structures Diamond Crystal Structure Silicon Crystal Structure Silicon Crystals and Atomic Packing Factors Crystal Order and Perfection Crystal Orientations and Planes Influence of Dopants and Impurities in Silicon Crystals Summary References Different Techniques for Growing Single-Crystal Silicon Introduction Bridgman Crystal Growth Technique Czochralski Crystal Growth/Pulling Technique Crucible Choice for Molten Silicon Chamber Temperature Profile Seed Selection for Crystal Pulling Environmental and Ambient Control in the Crystal Chamber Crystal Pull Rate and Seed/Crucible Rotation Dopant Addition for Growing Doped Crystals Methods for Continuous Czochralski Crystal Growth Impurity Segregation between Liquid and Grown Silicon Crystals Crystal Growth Striations Use of a Magnetic Field in the Czochralski Growth Technique Large-Area Silicon Crystals for VLSI and ULSI Applications Post-Growth Thermal Gradient and Crystal Cooling after Pull-Out Float-Zone Crystal Growth Technique Seed Selection Environment and Chamber Ambient Control Heating Mechanisms and RF Coil Shape Crystal Growth Rate and Seed Rotation Dopant Distribution in Growing Crystals Impurity Segregation between Liquid and Grown Silicon Crystals Use of Magnetic Field for Float-Zone Growth Large Area Silicon Crystals and Limitations of Shape and Size Thermal Gradient and Post-Growth Crystal Cooling Zone Refining of Single-Crystal Silicon Other Silicon Crystalline Structures and Growth Techniques Silicon Ribbons Silicon Sheets Silicon Whiskers and Fibers Silicon in Circular and Spherical Shapes Silicon Hollow Tubes Casting of Polycrystalline Silicon for Photovoltaic Applications Summary References From Silicon Ingots to Silicon Wafers Introduction Radial Resistivity Measurements Boule Formation, Identification of Crystal Orientation, and Flats Ingot Slicing Mechanical Lapping of Wafer Slices Edge Profiling of Slices Chemical Etching and Mechanical Damage Removal Chemimechanical Polishing for Planar Wafers Surface Roughness and Overall Wafer Topography Megasonic Cleaning Final Cleaning and Inspection Summary References Evaluation of Silicon Wafers Introduction Acoustic Laser Probing Technique Atomic-Force Microscope Studies on Surfaces Auger Electron Spectroscopic Studies Chemical Staining and Etching Techniques Contactless Characterization Deep-Level Transient Spectroscopy Defect Decoration by Metals Electron Beam and High-Energy Electron Diffraction Studies Flame Emission Spectrometry Four-Point Probe Technique for Resistivity Measurement and Mapping Fourier Transform Infrared Spectroscopy Measurements for Impurity Identification Gas Fusion Analysis Hall Mobility Mass Spectra Analysis Minority Carrier Diffusion Length/Lifetime/Surface Photovoltage Optical Methods for Impurity Evaluation Photoluminescence Method for Determining Impurity Concentrations Gamma-Ray Diffractometry Scanning Electron Microscopy for Defect Analysis Scanning Optical Microscope Secondary Ion Mass Spectrometer for Impurity Distribution Spreading Resistance and Two-Point Probe Measurement Technique Stress Measurements Transmission Electron Microscopy van der Pauw Resistivity Measurement Technique for Irregular-Shaped Wafers X-Ray Technique for Crystal Perfection and Dislocation Density Summary References Resistivity and Impurity Concentration Mapping of Silicon Wafers Introduction Electrically Active and Inactive Impurities Surface Mapping and Concentration Contours Surface Roughness Mapping on a Complete Wafer Summary References Impurities in Silicon Wafers Effect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices Intentional Dopant Impurities in Silicon Wafers Aluminum Antimony Arsenic Boron Gallium Phosphorus Unintentional Dopant Impurities in Silicon Wafers Carbon Chromium Copper Germanium Gold Helium Hydrogen Iron Nickel Nitrogen Oxygen Tin Other Metallic Impurities Summary References Defects in Silicon Wafers Introduction Impact of Defects in Silicon Devices and Structures Point Defects and Vacancies Line Defects Bulk Defects and Voids Dislocations and Screw Dislocations Swirl Defects Stacking Faults Precipitations Surface Pits/Crystal-Originated Particles Grown Vacancies and Defects Thermal Donors Slips, Cracks, and Shape Irregularities Stress, Bowing, and Warpage Summary References Silicon Wafer Preparation for VLSI and ULSI Processing Introduction Purity of Chemicals Used for Silicon Processing Degreasing of Silicon Wafers Removal of Metallic and Other Impurities Gettering of Metallic Impurities Denuding of Silicon Wafers Neutron Irradiation Argon Annealing of Wafers Hydrogen Annealing of Wafers Final Cleaning, Rinsing, and Wafer Drying Summary References Packing of Silicon Wafers Packing of Fully Processed Blank Silicon Wafers Storage of Wafers and Control of Particulate Contamination Storage of Wafers and Control of Particulate Contamination with Process-Bound Wafers Summary References Index

Deep Etching of Single- and Polycrystalline Silicon with High Speed, High Aspect Ratio, High Uniformity, and 3D Complexity by Electric Bias-Attenuated Metal-Assisted Chemical Etching (EMaCE)

Abstract: In this work, a novel wet silicon (Si) etching method, electric bias-attenuated metal-assisted chemical etching (EMaCE), is demonstrated to be readily available for three-dimensional (3D) electronic integration, microelectromechinal systems, and a broad range of 3D electronic components with low cost. On the basis of the traditional metal-assisted chemical etching process, an electric bias was applied to the Si substrate in EMaCE. The 3D geometry of the etching profile was effectively controlled by the bias in a real-time manner. The reported method successfully fabricated an array of over 10 000 vertical holes with diameters of 28 μm on 1 cm2 silicon chips at a rate of up to 11 μm/min. The sidewall roughness was kept below 50 nm, and a high aspect ratio of over 10:1 was achieved. The 3D geometry could be attenuated by the variable applied bias in real time. Vertical deep etching was realized on (100)-, (111)-Si, and polycrystalline Si substrates. Complex features with lateral dimensions of 0.8–500 μm wer...

Improving The Efficiency Of PolycrystallineSolar Panel Via Water Immersion Method

Abstract: Cooling of the solar cells is a critical issue, especially when designing concentrating photovoltaic (PV) systems. In the present work, the cooling of a photovoltaic panel via Water immersion technique is investigated. The aim of this project is to optimize the efficiency of a solar panel by submerged it in distillated water at different depths. Experiment is done for polycrystalline silicon panel. An evident increase of efficiency is found with increasing the water depth. Results are discussed; thermal drift has been reduced and the solar panel efficiency has increased by about 11% at water depth 6 cm.

Extreme Light Absorption by Multiple Plasmonic Layers on Upgraded Metallurgical Grade Silicon Solar Cells

Abstract: We fabricate high-efficiency, ultrathin (∼12 μm), flexible, upgraded metallurgical-grade polycrystalline silicon solar cells with multiple plasmonic layers precisely positioned on top of the cell to dramatically increase light absorption. This scalable approach increases the optical absorptivity of our solar cells over a broad range of wavelengths, and they achieve efficiencies η ≈ 11%. Detailed studies on the electrical and optical properties of the developed solar cells elucidate the light absorption contribution of each individual plasmonic layer. Finite-difference time-domain simulations were also performed to yield further insights into the obtained results. We anticipate that the findings from this work will provide useful design considerations for fabricating a range of different solar cell systems.

An Improved Matlab-Simulink Model of PV Module considering Ambient Conditions

Abstract: A photovoltaic (PV) model is proposed on Matlab/Simulink environment considering the real atmospheric conditions and this PV model is tested with different PV panels technologies (monocrystalline silicon, polycrystalline silicon, and thin film). The meteorological data of Istanbul—the location of the study—such as irradiance, cell temperature, and wind speed are taken into account in the proposed model for each technology. Eventually, the power outputs of the PV module under real atmospheric conditions are measured for resistive loading and these powers are compared with the results of proposed PV model. As a result of the comparison, it is shown that the proposed model is more compatible for monocrystal silicon and thin-film modules; however, it does not show a good correlation with polycrystalline silicon PV module.

Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation

Abstract: A lateral polysilicon Bipolar Charge Plasma Transistor (poly-Si BCPT) on undoped recrystallized polycrystalline silicon which is compatible with the thin-film field effect transistor (TFT) fabrication is reported in this paper. Using calibrated two-dimensional device simulation, the electrical performance of the poly-Si BCPT is evaluated in detail by considering the position of the single grain boundary. Our simulation results demonstrate that the poly-Si BCPT has the potential to realize low-cost thin-film polycrystalline silicon bipolar transistors with large current gain and cut-off frequency making it suitable for a number of applications including the driver circuits of the displays.

Outdoor testing of photovoltaic modules during summer in taxila, pakistan

Abstract: An experimental study has been carried out to measure the performance of commercially available photovoltaic modules during summer months in the climate of Taxila, near the capital of Pakistan. The modules used in the study are monocrystalline silicon (c-Si), polycrystalline silicon (p-Si) and single junction amorphous silicon (a-Si). The analysis has been focused on the measurement of module efficiency, performance ratio and temperature of each module at actual operating conditions using outdoor monitoring facility. The measured results are compared with the already published data of peak winter month at the same site. Overall, the monocrystalline module showed high average module efficiency while amorphous silicon module was better in term of average performance ratio. Furthermore, the module efficiency and performance ratio has shown decreasing trend with increase of module temperature. It was found that modules have much higher temperature in summer months (about 20°C higher) and showed low efficiency and performance ratio than peak winter month. The average ambient temperature varied from 18.1°C to 38.6°C from winter to summer.

Grain Boundary Engineering for Improved Thin Silicon Photovoltaics

Abstract: In photovoltaic devices, the bulk disorder introduced by grain boundaries (GBs) in polycrystalline silicon is generally considered to be detrimental to the physical stability and electronic transport of the bulk material. However, at the extremum of disorder, amorphous silicon is known to have a beneficially increased band gap and enhanced optical absorption. This study is focused on understanding and utilizing the nature of the most commonly encountered Σ3 GBs, in an attempt to balance incorporation of the advantageous properties of amorphous silicon while avoiding the degraded electronic transport of a fully amorphous system. A combination of theoretical methods is employed to understand the impact of ordered Σ3 GBs on the material properties and full-device photovoltaic performance.

Image analysis of polycrystalline solar cells and modeling of intergranular and transgranular cracking

Abstract: An innovative image analysis technique is proposed to process real solar cell pictures, identify grains and grain boundaries in polycrystalline silicon, and finally generate finite element meshes. Using a modified intrinsic cohesive zone model approach to avoid mesh dependency, nonlinear finite element simulations show how grain boundaries and silicon bulk properties influence the crack pattern. Numerical results demonstrate a prevalence of transgranular over intergranular cracking for similar interface fracture properties of grains and grain boundaries, in general agreement with the experimental observation.

Paradoxical Enhancement of the Power Factor of Polycrystalline Silicon as a Result of the Formation of Nanovoids

Abstract: Hole-containing silicon has been regarded as a viable candidate thermoelectric material because of its low thermal conductivity. However, because voids are efficient scattering centers not just for phonons but also for charge carriers, achievable power factors (PFs) are normally too low for its most common form, i.e. porous silicon, to be of practical interest. In this communication we report that high PFs can, indeed, be achieved with nanoporous structures obtained from highly doped silicon. High PFs, up to a huge 22 mW K−2 m−1 (more than six times higher than values for the bulk material), were observed for heavily boron-doped nanocrystalline silicon films in which nanovoids (NVs) were generated by He+ ion implantation. In contrast with single-crystalline silicon in which He+ implantation leads to large voids, in polycrystalline films implantation followed by annealing at 1000°C results in homogeneous distribution of NVs with final diameters of approximately 2 nm and densities of the order of 1019 cm−3 with average spacing of 10 nm. Study of its morphology revealed silicon nanograins 50 nm in diameter coated with 5-nm precipitates of SiB x . We recently reported that PFs up to 15 mW K−2 m−1 could be achieved for silicon–boron nanocomposites (without NVs) because of a simultaneous increase of electrical conductivity and Seebeck coefficient. In that case, the high Seebeck coefficient was achieved as a result of potential barriers on the grain boundaries, and high electrical conductivity was achieved as a result of extremely high levels of doping. The additional increase in the PF observed in the presence of NVs (which also include SiB x precipitates) might have several possible explanations; these are currently under investigation. Experimental results are reported which might clarify the reason for this paradoxical effect of NVs on silicon PF.

Solar cell emitter region fabrication using ion implantation

Abstract: Methods of fabricating solar cell emitter regions using ion implantation, and resulting solar cells, are described. In an example, a back contact solar cell includes a crystalline silicon substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region is disposed above the crystalline silicon substrate. The first polycrystalline silicon emitter region is doped with dopant impurity species of a first conductivity type and further includes ancillary impurity species different from the dopant impurity species of the first conductivity type. A second polycrystalline silicon emitter region is disposed above the crystalline silicon substrate and is adjacent to but separated from the first polycrystalline silicon emitter region. The second polycrystalline silicon emitter region is doped with dopant impurity species of a second, opposite, conductivity type. First and second conductive contact structures are electrically connected to the first and second polycrystalline silicon emitter regions, respectively.