Showing papers on "Polycrystalline silicon published in 2022"

Dye‐sensitized solar cells as promising candidates for underwater photovoltaic applications

Abstract: Harvesting solar energy using photovoltaic (PV) cells is the simplest, efficient, and reliable approach to power marine electronics. Installing PV above or under water provides cooling and cleaning to sustain the power conversion efficiency. Previous work on commercially available silicon‐based PV quantified the performance of PV with different submerged environments and showed promising results in harvesting available underwater solar energy. Subsequent, theoretical studies point to enormous potential of using wide‐band‐gap PV in underwater conditions. With this motivation, herein for the first time, a dye‐sensitized solar cells (DSSCs) employing wide‐bandgap ruthenium sensitizers (1.8 eV) have been tested under submerged conditions. The DSSCs were characterized under submerged conditions up to 20 cm. Four replicates provided data detailing DSSCs potential for underwater PV applications when compared with the previously collected data for monocrystalline, polycrystalline, and amorphous silicon PV. Although the light intensity under water decreases with an increase in depths, the rate of decrease in power output for DSSCs was only 40.68%, which was less than the traditional monocrystalline and polycrystalline silicon PV by approximately 20–25%. Also, compared with amorphous silicon PV, DSSCs showed a slightly better performance by 2–3%, clearly displaying the capability of DSSCs to harvest indirect/diffused lights in comparison with the conventional PVs. Compared with the conventional PVs, indigenously fabricated DSSCs showed tremendous relative increase in performance in underwater conditions. Further work is underway to further optimize DSSCs even though it can be concluded that with added advantages of simple fabrication process and cost‐effectiveness, DSSCs have enormous future potential for underwater PV applications.

Local Enhancement of Dopant Diffusion from Polycrystalline Silicon Passivating Contacts.

Abstract: Passivating contacts consisting of heavily doped polycrystalline silicon (poly-Si) and ultrathin interfacial silicon oxide (SiOx) films enable the fabrication of high-efficiency Si solar cells. The electrical properties and working mechanism of such poly-Si passivating contacts depend on the distribution of dopants at their interface with the underlying Si substrate of solar cells. Therefore, this distribution, particularly in the vicinity of pinholes in the SiOx film, is investigated in this work. Technology computer-aided design (TCAD) simulations were performed to study the diffusion of dopants, both phosphorus (P) and boron (B), from the poly-Si film into the Si substrate during the annealing process typically applied to poly-Si passivating contacts. The simulated 2D doping profiles indicate enhanced diffusion under pinholes, yielding deeper semicircular regions of increased doping compared to regions far removed from the pinholes. Such regions with locally enhanced doping were also experimentally demonstrated using high-resolution (5-10 nm/pixel) scanning spreading resistance microscopy (SSRM) for the first time. The SSRM measurements were performed on a variety of poly-Si passivating contacts, fabricated using different approaches by multiple research institutes, and the regions of doping enhancement were detected on samples where the presence of pinholes had been reported in the related literature. These findings can contribute to a better understanding, more accurate modeling, and optimization of poly-Si passivating contacts, which are increasingly being introduced in the mass production of Si solar cells.

Monolithic Perovskite/Silicon Tandem Solar Cells Fabricated Using Industrial p‐Type Polycrystalline Silicon on Oxide/Passivated Emitter and Rear Cell Silicon Bottom Cell Technology

Abstract: Combining a perovskite top cell with a conventional passivated emitter and rear cell (PERC) silicon bottom cell in a monolithically integrated tandem device is an economically attractive solution to boost the power conversion efficiency (PCE) of silicon single‐junction technology. Proof‐of‐concept perovskite/silicon tandem solar cells using high‐temperature stable bottom cells featuring a polycrystalline silicon on oxide (POLO) front junction and a PERC‐type passivated rear side with local aluminum‐p+ contacts are reported. For this PERC/POLO cell, a process flow that is compatible with industrial, mainstream PERC technology is implemented. Top and bottom cells are connected via a tin‐doped indium oxide recombination layer. The recombination layer formation on the POLO front junction of the bottom cell is optimized by postdeposition annealing and mitigation of sputter damage. The perovskite top cell is monolithically integrated in a p−i−n junction device architecture. Proof‐of‐concept tandem cells demonstrate a PCE of up to 21.3%. Based on the experimental findings and supporting optical simulations, major performance enhancements by process and layer optimization are identified and a PCE potential of 29.5% for these perovskite/silicon tandem solar cells with PERC‐like bottom cell technology is estimated.

Monolithic Perovskite/Silicon Tandem Solar Cells fabricated using industrial p‐type POLO/PERC Silicon Bottom Cell Technology

Abstract: Combining a perovskite top cell with a conventional passivated emitter and rear cell (PERC) silicon bottom cell in a monolithically integrated tandem device is an economically attractive solution to boost the power conversion efficiency (PCE) of silicon single-junction technology. Proof-of-concept perovskite/silicon tandem solar cells using high-temperature stable bottom cells featuring a polycrystalline silicon on oxide (POLO) front junction and a PERC-type passivated rear side with local aluminum-p+ contacts are reported. For this PERC/POLO cell, a process flow that is compatible with industrial, mainstream PERC technology is implemented. Top and bottom cells are connected via a tin-doped indium oxide recombination layer. The recombination layer formation on the POLO front junction of the bottom cell is optimized by postdeposition annealing and mitigation of sputter damage. The perovskite top cell is monolithically integrated in a p−i−n junction device architecture. Proof-of-concept tandem cells demonstrate a PCE of up to 21.3%. Based on the experimental findings and supporting optical simulations, major performance enhancements by process and layer optimization are identified and a PCE potential of 29.5% for these perovskite/silicon tandem solar cells with PERC-like bottom cell technology is estimated.

Performance comparison of mono and polycrystalline silicon solar photovoltaic modules under tropical wet and dry climatic conditions in east-central India

Abstract: This work focuses on the performance comparison of monocrystalline and polycrystalline Si solar photovoltaic (SPV) modules under tropical wet and dry climatic conditions in east-central India (21.16° N 81.65° E, Raipur, Chhattisgarh). This study would help to select the SPV module for system installation in the east-central part of the country. For comparative analysis, we used performance ratio (PR) and efficiency as figures of merit. The plane-of-array (POA) irradiance was used to determine the efficiency of the modules. The decomposition and transposition models calculated the POA values from the measured global horizontal irradiance. The data were analysed systematically for 6 months in the non-rainy season, from October 2020 to March 2021. Special attention was given to solar irradiance, ambient temperature and module temperature—the parameters that affect the performance of PV modules. The month of October showed the highest variation in irradiance and temperature. The highest average module temperatures (51–52°C) were observed in October–November, while the lowest average module temperatures (34°C for mono-Si and 36°C for poly-Si) were observed in December. The highest value of average monthly POA irradiance (568 W/m2) was observed in February and the lowest (483 W/m2) in December. The results showed that the monocrystalline SPV module performed better than the polycrystalline module under all weather conditions. The maximum observed values of mono-Si and poly-Si panel PRs were 0.89 and 0.86, respectively, in December. Thermal losses were higher with higher module temperatures in October and November, and lower in December due to lower temperatures. The energy yield was calculated from the measured data and compared with PVSyst simulations.

Recent Advances on Thermoelectric Silicon for Low-Temperature Applications

Abstract: Silicon is the most widely used functional material, as it is geo-abundant and atoxic. Unfortunately, its efficiency as a thermoelectric material is very poor. In this paper, we present and discuss advances of research on silicon and related materials for thermoelectric applications, mostly focusing on the comparison between the two strategies deployed to increase its performance, namely either reducing its thermal conductivity or, in polycrystalline materials, increasing its power factor. Special attention will be paid to recent results concerning silicon thin films. The enhancement of Si performances has motivated efforts to develop integrated heat microharvesters operating around room temperature, which will be reviewed also in view of their applications to power wireless sensors for the Internet of Things.

Silicon solar cells with passivating contacts: Classification and performance

Abstract: The year 2014 marks the point when silicon solar cells surpassed the 25% efficiency mark. Since then, all devices exceeding this mark, both small and large area, with contacts on both sides of the silicon wafer or just at the back, have utilized at least one passivating contact. Here, a passivating contact is defined as a group of layers that simultaneously provide selective conduction of charge carriers and effective passivation of the silicon surface. The widespread success of passivating contacts has prompted increased research into ways in which carrier‐selective junctions can be formed, yielding a diverse range of approaches. This paper seeks to classify passivating contact solar cells into three families, according to the material used for charge‐carrier selection: doped amorphous silicon, doped polycrystalline silicon, and metal compounds/organic materials. The paper tabulates their current efficiency values, discusses distinctive features, advantages, and limitations, and highlights promising opportunities going forth towards even higher conversion efficiencies.

Influence of Silicon Dioxide-Titanium Dioxide Antireflective Electrosprayed Coatings on Multicrystalline Silicon Cells

Abstract: This research work primarily focuses on enhancing the power conversion efficiency (PCE) of polycrystalline silicon solar cells by using a single-layer and a double-layered antireflection coating deposited through the electrospraying technique. The usage of titanium dioxide and silicon dioxide as antireflection coating materials has shown a significant increase in the optical and electrical properties of solar cells under open and controlled light sources. The sample with TiO2 as a base layer and SiO2 as the top layer (sample B-IV) exhibited a maximum PCE of 18.90% in direct sunlight and 21.19% in a neodymium setup with cell temperatures of 40°C and 52.1°C, respectively. Sample B-IV has also shown the lowest resistivity of 3.1 × 10−3 Ω·cm among the coated samples. Also, an increase of 11.6% light transmittance and a reduction of 9.6% light reflectance were exerted by sample B-IV. The results obtained from different analysis proves that TiO2/SiO2 was an appropriate antireflection coating material for enhancing the PCE of the polycrystalline silicon solar cell.

Impurity Gettering in Polycrystalline‐Silicon Based Passivating Contacts—The Role of Oxide Stoichiometry and Pinholes

Abstract: Polycrystalline‐silicon/oxide (poly‐Si/SiOx) passivating contacts for high efficiency solar cells exhibit excellent surface passivation, carrier selectivity, and impurity gettering effects. However, the ultrathin SiOx interlayer can act as a diffusion barrier for metal impurities and this potentially slows down the overall gettering rate of the poly‐Si/SiOx structures. Herein, the factors that determine the blocking effects of the SiOx interlayers are identified and investigated by examining two general types of the SiOx interlayers: 1.3 nm ultrathin tunneling SiOx with negligible pinholes and 2.5 nm SiOx with thermally created pinholes. Iron is used as tracer impurity in silicon to quantify the gettering rate. By fitting the experimental gettering kinetics by a diffusion‐limited segregation gettering model, the blocking effects of the SiOx interlayers are quantified by a transport parameter. Both the oxide stoichiometry and pinhole density affect the effective transport of iron through SiOx interlayers. The oxide stoichiometry depends strongly on the oxidation method, while the pinhole density is affected by the activation temperature, doping concentration, doping technique, and possibly the dopant type as well. To enable a fast gettering process during typical high‐temperature formation of the poly‐Si/SiOx structures, a SiOx interlayer that is less stoichiometric or with a higher pinhole density is preferred.

Gate driver with low‐temperature polycrystalline silicon and oxide thin‐film‐transistor circuits for low power consumption and narrow bezel AMOLED displays

Abstract: We propose a novel gate driver circuit using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistors (TFTs). The proposed circuit consists of only six TFTs, four p‐type LTPS, and two n‐type a‐IGZO TFTs, without capacitor. The proposed circuit operates well when oxide TFTs have threshold voltage (VTH) of −7.5 V, which is very depletion mode. Without bootstrapping, low gate bias stress occurs on TFTs in the proposed circuit. With dual gate (DG) structure of oxide TFTs, the stability of the proposed circuit is improved. In addition, by utilizing extremely low off‐state current of oxide TFTs, ultra‐low power consumption can be achieved. The total power consumption of the proposed gate driver is less than 100 mW under a‐IGZO TFT's VTH of −6 V at 120 Hz 4k (3,840 × 2,160) resolution display. The fabricated circuit works perfectly at a pulse width of 1 μs equivalent to operating speed of 500 kHz. The proposed circuit can be applied to ultra‐high definition (UHD) and narrow bezel AMOLED display.

Low-Frequency Noise in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Abstract: In this work, low-frequency noise (LFN) of bridged-grain (BG) polycrystalline silicon thin-film transistors (TFTs) is characterized and studied for the first time. The noise power spectral density (PSD) of drain current follows the classical 1/ ${f}$ noise theory. The carrier number with the correlated mobility fluctuation model dominates the device 1/ ${f}$ noise. Compared with normal TFTs, BG TFTs show a much smaller level of LFN, which is mainly attributed to grain boundary (GB) barrier lowering and trap density reduction.

Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

Abstract: In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage ( $\text{V}_{\text {th}}$ ) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a $\text{V}_{\text {th}}$ shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.

On analytical estimates of the effective elastic properties of polycrystalline silicon

Abstract: Several analytical approaches can be utilized to estimate the elastic properties of polycrystalline silicon. In experimental studies, the notion of an macroscopically isotropic aggregate is introduced while the single crystals obey cubic symmetry. We here give a synopsis on analytical approaches to predict elastic properties and apply them to estimate effective parameters of polycrystalline silicon. Here, the predictions are based on the parameters associated with shear solely. The results are juxtaposed in terms of the approaches applied, while different measures are introduced for evaluation. In comparison with experimental findings, the geometric mean implies a reasonable estimation for the elastic properties of polycrystalline silicon.