Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Flowable chips and methods for the preparation and use of same, and apparatus for use in the methods

Abstract: A method for recharging a crucible with polycrystalline silicon comprises adding flowable chips to a crucible used in a Czochralski-type process. Flowable chips are polycrystalline silicon particles made from polycrystalline silicon prepared by a chemical vapor deposition process, and flowable chips have a controlled particle size distribution, generally nonspherical morphology, low levels of bulk impurities, and low levels of surface impurities. Flowable chips can be added to the crucible using conventional feeder equipment, such as vibration feeder systems and canister feeder systems.

Method for fabricating semiconductor device having gate electrode with polymetal structure of polycrystalline silicon film and metal film

Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10 , spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12 , a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16 , a metal nitride film 20 formed on the polycrystalline silicon film 30 , and a metal film 22 formed on the barrier metal film 20 . Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.

The determination of grain‐boundary recombination rates by scanned spot excitation methods

Abstract: Laser‐ and electron‐beam induced‐current techniques have been used to determine minority carrier diffusion lengths and grain‐boundary recombination velocities in polycrystalline silicon. Data obtained on a variety of grain boundaries appear to be in good agreement with the recent calculations by Zook.

Very high-cycle fatigue failure in micron-scale polycrystalline silicon films : Effects of environment and surface oxide thickness

Abstract: Fatigue failure in micron-scale polycrystalline silicon structural films, a phenomenon that is not observed in bulk silicon, can severely impact the durability and reliability of microelectromechanical system devices. Despite several studies on the very high-cycle fatigue behavior of these films (up to 1012cycles), there is still an on-going debate on the precise mechanisms involved. We show here that for devices fabricated in the multiuser microelectromechanical system process (MUMPs) foundry and Sandia Ultra-planar, Multi-level MEMS Technology (SUMMiT V™) process and tested under equi-tension/compression loading at ∼40kHz in different environments, stress-lifetime data exhibit similar trends in fatigue behavior in ambient room air, shorter lifetimes in higher relative humidity environments, and no fatigue failure at all in high vacuum. The transmission electron microscopy of the surface oxides in the test samples shows a four- to sixfold thickening of the surface oxide at stress concentrations after fatigue failure, but no thickening after overload fracture in air or after fatigue cycling in vacuo. We find that such oxide thickening and premature fatigue failure (in air) occur in devices with initial oxide thicknesses of ∼4nm (SUMMiT V™) as well as in devices with much thicker initial oxides ∼20nm (MUMPs). Such results are interpreted and explained by a reaction-layer fatigue mechanism. Specifically, moisture-assisted subcritical cracking within a cyclic stress-assisted thickened oxide layer occurs until the crack reaches a critical size to cause catastrophic failure of the entire device. The entirety of the evidence presented here strongly indicates that the reaction-layer fatigue mechanism is the governing mechanism for fatigue failure in micron-scale polycrystalline silicon thin films.

Interfacial Structure of Tungsten Layers Formed by Selective Low Pressure Chemical Vapor Deposition

Abstract: We have analyzed the interfacial structure of selectively deposited LPCVD tungsten on monocrystalline silicon, polycrystalline silicon, and polycrystalline aluminum substrates. Cross-sectional specimens were examined by transmission electron microscopy to determine the amount of substrate consumed by the selective deposition process and to assess the degree of lateral encroachment under masking SiO/sub 2/ layers for different conditions of deposition and surface preparation. The tungsten-silicon interfacial structure was found to depend strongly on the initia surface preparation. Immersion in a dilute HF solution resulted in a smooth interface, while a glow-discharge treatment (CF/sub 4/ + O/sub 2/) led to highly irregular interfaces, which, in extreme cases, contained tunnels extending 1 ..mu..m or more into the silicon substrate. Layers formed in WF/sub 6/ plus H/sub 2/ were found to consist of two layers, of which the lower layer i formed by the substrate reduction of WF/sub 6/.