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Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the properties of thermally grown silicon dioxide films on n+polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms.
Abstract: The properties of thermally grown silicon dioxide films on n+polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms. All of the above electrical parameters are found to be degraded by any increase in the degree of surface roughness at the oxide-polysilicon interface. Our results suggest that a significant improvement in the insulating properties of the SiO 2 films can be achieved if the polysilicon is initially deposited in the amorphous phase at 560°C rather than the polycrystalline phase at 620°C. For example, for dry-oxidized diffusion-doped films, there is an increase in oxide breakdown field from 3.0 MV . cm-1to 6.2 MV . cm-1, and a reduction in leakage (Fowler-Nordheim) current of two orders of magnitude. Furthermore, it is shown that the long-term reliability of n+polysilicon/SiO 2 /n+polysilicon structures is directly related to the degree of interface texture; i.e., a smoother interface will result in a significant reduction in electrical wearout and an increase in time to failure.

59 citations

Journal ArticleDOI
TL;DR: In this paper, the effects of O2 and N2 addition on the etch rate and surface chemistry were established using various CF4/O2/N2 gas compositions.
Abstract: The remote plasma chemical dry etching of polycrystalline silicon was investigated using various CF4/O2/N2 gas compositions The effects of O2 and N2 addition on the etch rate and surface chemistry were established Admixing O2 to CF4 increases the gas phase fluorine density and increases the etch rate by roughly sevenfold to a maximum at an O2/CF4 ratio of 015 The addition of small amounts of N2 (N2/CF4=005) can again double this etch rate maximum Strong changes in surface chemistry were also seen as a result of N2 addition to CF4/O2 Real-time ellipsometry and atomic force micro-roughness measurements reveal that nitrogen addition at low O2/CF4 ratios leads to the smoothing of surfaces, but to increased oxidation at high O2/CF4 ratios Based on etch rate data and gas phase species analysis, we propose that NO plays an important role in the overall etching reaction Variable tube lengths separated the reaction chamber from the discharge These tubes were lined with either quartz or Teflon liners In

59 citations

Journal ArticleDOI
TL;DR: In this paper, the authors measured the residual strain in polycrystalline silicon thin films with high spatial resolution (∼5 μm) by Raman spectroscopy and found that a major component of the stress in the film arises from pinning of the silicon at the silicon fused silica interface at the solidification temperature followed by differential thermal contraction.
Abstract: Residual strain in cw laser‐crystallized silicon thin films has been measured with high spatial resolution (∼5 μm) by Raman spectroscopy. Thin films of polycrystalline silicon were defined into moated islands and patterned stripes on fused silica substrates and encapsulated with silicon nitride. Raman scattering was used to measure local strain at various points in and near crystallized islands, and the results reveal that the silicon film is under tension. The observations indicate that a major component of the stress in the film arises from pinning of the silicon at the silicon‐fused silica interface at the solidification temperature followed by differential thermal contraction.

59 citations

Patent
13 Jun 1994
TL;DR: In this paper, a process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided, where a thin insulating layer is formed on the surface of a substrate.
Abstract: A process of fabricating a semiconductor device on a substrate with closely spaced high density conductive lines is provided. A thin insulating layer is formed on the surface of a substrate. Next, a blanket conductive layer and a blanket masking layer are deposited over the first insulating layer. Using conventional photolithography processes and plasma etching, elongated spaced parallel masking lines with vertical sidewalls are formed in the masking layer. A blanket polycrystalline silicon layer is deposited on the masking lines and the exposed areas of the conductive layer. Next, the blanket polycrystalline silicon layer is anisotrophically etched to form spacers on the vertical sidewalls of the masking lines. A second planarized masking layer is formed over the spacers and masking lines. The polycrystalline silicon spacers and the underlying first polycrystalline silicon layer are anisotrophically etched to form the closely spaced conductive lines in the first polycrystalline silicon layer. A coating of electrically isolating material is formed between and over the conductive lines.

59 citations

Journal ArticleDOI
TL;DR: In this article, the dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors was analyzed using device simulation.
Abstract: Dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) has been analyzed using device simulation. In the linear region, degradation is similar wherever the grain boundary is located. On the other hand, in the saturation region, degradation is less when the grain boundary is in the pinch-off region near the drain edge and degradation is similar when the grain boundary is elsewhere. Although this dependence is similar to the dependence on the trap location in single-crystal silicon transistors, the mechanism is different. This dependence in poly-Si TFTs is because the coulombic potential barrier caused by the grain boundary is lowered in the high electric field in the pinch-off region. This is a kind of Poole–Frenkel effect.

59 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202343
2022130
2021122
2020313
2019498
2018534