Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Effect of dust deposition on the performance of photovoltaic modules in Taxila, Pakistan

Abstract: The air borne dust deposited on the surface of photovoltaic module influence the transmittance of solar radiations from the photovoltaic module’s glazing surface. This experimental work aimed to investigate the effect of dust deposited on the surface of two different types of photovoltaic modules (monocrystalline silicon and polycrystalline silicon). Two modules of each type were used and one module from each pair was left exposed to natural atmosphere for three months of winter in Taxila, Pakistan. Systematic series of measurements were conducted for the time period of three months corresponding to the different dust densities. The difference between the output parameters of clean and dirty modules provided the information of percentage loss at different dust densities. The dust density deposited on the modules surface was 0.9867mg/cm2 at the end of the study. The results showed that dust deposition has strong impact on the performance of photovoltaic modules. The monocrystalline and polycrystalline modules showed about 20% and 16% decrease of average output power respectively compared to the clean modules of same type. It was found that the reduction of module efficiency (ηclean - ηdirty) in case of monocrystalline and polycrystalline module was 3.55% and 3.01% respectively. Moreover the loss of output power and module efficiency in monocrystalline module was more compared to the polycrystalline module.

Method to fabricate the thin film transistor

Abstract: Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si1-x -Gex) thin film transistors at low temperature and low thermal budget. Poly-Si and poly-Si1-x -Gex can be deposited by UHV/CVD without any anneal step. And due to the ultra low base pressure and ultraclean growth environment, the As-deposited poly films have low defect densities. However, the surface morphology retards the usage of the fabricating top-gate poly TFT's. In this invention, the CMP system is used for improving the surface morphology, high performance poly-Si and poly-Si1-x -Gex TFT's can be obtained.

A new poly-Si TFT with selectively doped channel fabricated by novel excimer laser annealing

Abstract: A new excimer laser annealing method, which results in a single grain boundary in the channel of polycrystalline silicon thin film transistor (poly-Si TFT), is proposed. The proposed method employs lateral grain growth through aluminum patterns on an amorphous silicon layer. The aluminum pattern acts as a selective beam mask and a lateral heat sink during the laser irradiation. Poly-Si TFTs fabricated by the proposed ELA method exhibit considerably improved characteristics, such as the high field effect mobility exceeding 240 cm/sup 2//V sec. The turn-off characteristics have also been improved by the field-reducing structure.

Nonvolatile semiconductor memory device

Abstract: PURPOSE:To obtain a large area floating gate composed of only one layer of a polycrystalline silicon layer by a method wherein a drain region and a source region are formed near a silicon substrate surface including the part of the substrate surface under an insulating film connected to a gate insulating film. CONSTITUTION:A drain region 17 which is to be a bit line for memory transistors M1 and M2 and a source region 18 which is to be a source line of the memory transistors M1 and M2 are formed as buried diffused regions. With this process, a source diffused layer 18 and a drain diffused layer 17 are extended onto the drain region 17 and the source region 18 without cutting off not only a main bit line 11, a main source line and a cell isolation region which makes cells independent from each other but also a polycrystalline silicon layer which is to be a floating gate 15. With this constitution, the source/drain and the floating gate can be formed in a self-alignment manner and, further, a large area floating gate composed of only one layer of a polycrystalline silicon layer can be obtained.

A model for conduction in polycrystalline silicon—Part II: Comparison of theory and experiment

Abstract: In the preceding paper [1], a new phenomenological model for the electrical conduction in polycrystalline silicon was developed. Electrical conduction in polycrystalline silicon was shown to be controlled by dopant segregation, carrier trapping, and carrier tunneling through the grain boundaries. In this paper, the theoretical model is compared to experiment. The electrical behavior of polycrystalline silicon is shown to be influenced by the properties of the grain boundaries. In arsenic and phosphorus-doped polycrystalline-silicon films the grain boundaries are best modeled by rectangular barriers with a height of 0.66 eV and an approximate width of 7 A. The width of the grain-boundary barriers and the density of carrier trapping states are found to be weak functions of the dopant species and sample processing. The resistivity is found to be a strong function of dopant concentration, dopant species, and processing history at low and intermediate dopant concentrations, and the model can be used to predict this behavior.