Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Process for manufacturing integrated bi-polar transistors of very small dimensions

Abstract: A process is provided for manufacturing bi-polar transistors integrated on silicon. To form transistors of very small dimensions, a layer of polycrystalline silicon is deposited (after a localized oxidization step) which is etched and which is doped so as to serve as doping source for P+ extrinsic base regions of the transistor. After doping of the P intrinsic base, the oxide and/or nitride is then deposited at low pressure which is implanted with an impurity facilitating dissolution thereof. On the vertical walls of the polycrystalline silicon around the base, the nitride is not dissolved. Elsewhere it is easily dissolved. Advantage is taken of the oxide or nitride thickness which remains to form by diffusion of an N+ emitter region which will not extend laterally as far as the P+ type extrinsic base but which will allow to remain an intrinsic base of very small thickness. The emitter diffusion may take place through a second polycrystalline silicon layer.

Fatigue failure in thin-film polycrystalline silicon is due to subcritical cracking within the oxide layer

Abstract: It has been established that microelectromechanical systems created from polycrystalline silicon thin films are subject to cyclic fatigue. Prior work by the authors has suggested that although bulk silicon is not susceptible to fatigue failure in ambient air, fatigue in micron-scale silicon is a result of a “reaction-layer” process, whereby high stresses induce a thickening of the post-release oxide at stress concentrations such as notches, which subsequently undergoing moisture-assisted cracking. However, there exists some controversy regarding the post-release oxide thickness of the samples used in the prior study. In this letter, we present data from devices from a more recent fabrication run that confirm our prior observations. Additionally, new data from tests in high vacuum show that these devices do not fatigue when oxidation and moisture are suppressed. Each of these observations lends credence to the “reaction-layer” mechanism.

Dram cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for a capacitive surface

Abstract: A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.

Semiconductor integrated circuit device and production method thereof

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer

Abstract: A contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.