Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Effect of arsenic segregation on the electrical properties of grain boundaries in polycrystalline silicon

Abstract: Equilibrium arsenic segregation to the grain boundaries of polycrystalline silicon was measured directly by x‐ray microanalysis in the temperature range 700–1000 °C. A direct link was observed between arsenic segregation and resistivity. Increasing arsenic segregation at the lower annealing temperatures is consistent with an observed increase in resistivity. Fitting the enhancement levels at various temperatures with the McLean segregation isotherm, a binding energy of 0.65 eV/atom and a boundary saturation limit of 12 at. % for arsenic was obtained. A model for the effect of the segregation of arsenic to silicon grain boundaries is proposed. Segregation to boundary defects that cause trapping states can remove these interfacial traps, and segregation to other boundary sites can create a degenerately‐doped interfacial layer. The electrical consequences of this segregation are considered, and by comparison of the measured resistivity changes with temperatures with those predicted from these simple models it is proposed that the major contribution to the resistivity in heavily‐doped polycrystalline silicon comes from scattering of carriers by the high density of positive charge at the grain boundaries.

Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Large-Area Liquid Crystal Display

Abstract: A low-temperature poly-Si thin-film transistor (TFT), having inverted-staggered structure, has been developed successfully using excimer laser annealing and ion doping. This TFT is suitable for pixel transistors of large-area and high-resolution LCDs. The maximum process temperature of the TFT fabrication steps is less than 450°C, so the same glass substrate on which amorphous Si TFT arrays are formed can be used in this poly-Si TFT process. Furthermore, most of the procedures, equipment and thin-film materials used to fabricate amorphous Si TFTs are compatible with fabrication of the poly-Si TFTs. On the other hand, some investigation of the CMOS driver circuit has been done, and it has been found that the threshold voltage of these poly-Si TFTs can be controlled easily by lightly doping of B ion into the channel region using the ion doping system.

Growth, structure, and transport properties of thin (>10 nm) n-type microcrystalline silicon prepared on silicon oxide and its application to single-electron transistor

Abstract: Microcrystalline silicon (μc-Si:H) thin films were prepared at 300 °C on glass. Their structure and transport properties were studied in a wide range of film thickness ranging from 10 nm to 1 μm. The crystal fraction increases monotonously from ∼64% to ∼100% as film thickness increases. Electron mobility first increases with increasing film thickness at thicknesses smaller than 50 nm but saturates at larger thickness. This mobility behavior is explained by percolation transport through crystalline grains. These results are different from those obtained with preferentially oriented polycrystalline silicon films. It is related to the difference in the microstructure evolution in which subsequent film growth is influenced by the growth surface structure. A single-electron transistor fabricated in 30-nm-thick μc-Si:H exhibits Coulomb blockade effects at 4.2 K. This result indicates that amorphous phases which exist between crystalline grains behave as tunnel barrier for electrons.

Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer

Abstract: The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.