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Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.


Papers
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Journal ArticleDOI
01 Jan 2001
TL;DR: In this article, the authors used a ball-on-flat tribometer to measure surface roughness, friction, scratching and wear, indentation and boundary lubrication of bulk and treated silicon, polysilicon films and SiC films.
Abstract: Silicon-based microelectromechanical system (MEMS) devices are made from single-crystal silicon, polycrystalline silicon (polysilicon) films obtained by low-pressure chemical vapour deposition and certain ceramic films. For high-temperature applications, SiC films are being developed to replace polysilicon films. Tribology in the MEMS devices requiring relative motion is of importance. Atomic force microscopy/friction force microscopy (AFM/FFM) and nanoindentation techniques have been used for tribological studies on a microscale to nanoscale on materials of interest. These techniques have been used to study surface roughness, friction, scratching and wear, indentation and boundary lubrication of bulk and treated silicon, polysilicon films and SiC films, Macroscale friction and wear tests have also been conducted using the ball-on-flat tribometer. Measurements of microscale and macroscale frictional forces show that friction values on both scales of all the silicon samples are about the same for d...

51 citations

Proceedings ArticleDOI
07 May 2006
TL;DR: In this paper, the authors discuss some of the challenges faced in taking a polycrystalline silicon PV (photovoltaic) technology from R&D into production in such a short period of time.
Abstract: Crystalline Silicon on Glass (CSG) is a polycrystalline silicon PV (photovoltaic) technology that requires less than two micrometers of silicon thickness. At the time of this writing in April 2006, production of CSG solar panels is just beginning in a full-scale factory known as CSG-1. It was only 14 months ago, in February 2005, that ground-breaking for this factory occurred. At that time, the technology had only been demonstrated in 900-cm2 laboratory samples. This article discusses some of the challenges faced in taking a new PV technology from R&D into production in such a short period of time. Photos of the equipment used for each of the key steps are shown and the experience of commissioning the process is discussed.

51 citations

Patent
08 Jul 1980
TL;DR: In this paper, a process for self-aligned metal to silicon contacts and submicron contact-to-contact and metal-tometal spacing for field effect transistors is described.
Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces. Reactive ion etching of this second insulating layer moves the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation. The remaining polycrystalline layer is removed to leave the narrow regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes.

51 citations

Patent
20 Apr 1998
TL;DR: In this paper, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening, and side walls are formed on side surfaces of the gate electrode, and a silicide film is created on the gate electrodes and the source and drain regions.
Abstract: To form a recess defining a channel region in a SOI layer, a LOCOS oxide film is formed on a surface of the SO layer and then removed. Then, side walls of CVD oxide is formed on side surfaces defining an opening of a LOCOS oxide restraining film. Then, a gate oxide film is formed on an exposed surface of the SOI layer inside the opening. Then, CVD polycrystalline silicon is formed on the whole wafer surface, and then etched back to form a gate electrode of polycrystalline silicon inside the opening. At this time, a top surface of the gate electrode is at a level lower than a top surface of the restraining film. Next, the restraining film and the side walls are removed and ion implantation into the SOI layer is performed using the gate electrode as a mask to thereby form a source and a drain region. Then, side walls are formed on side surfaces of the gate electrode, and a silicide film is formed on the gate electrode and the source and drain regions.

51 citations

Journal ArticleDOI
TL;DR: In this paper, a very large density (∼109cm−2) of intragrain defects in polycrystalline silicon (pc-Si) layers obtained through aluminum-induced crystallization of amorphous Si and epitaxy was revealed.
Abstract: Defect etching revealed a very large density (∼109cm−2) of intragrain defects in polycrystalline silicon (pc-Si) layers obtained through aluminum-induced crystallization of amorphous Si and epitaxy. Electron-beam-induced current measurements showed a strong recombination activity at these defects. Cathodoluminescence measurements showed the presence of two deep-level radiative transitions (0.85 and 0.93eV) with a relative intensity varying from grain to grain. These results indicate that the unexpected quasi-independence on the grain size of the open-circuit voltage of these pc-Si solar cells is due to the presence of numerous electrically active intragrain defects.

51 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202343
2022130
2021122
2020313
2019498
2018534