Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Crystal Growth and Evaluation of Silicon for VLSI and ULSI

Abstract: Preface About the Author Introduction Silicon: The Semiconductor Why Single Crystals Revolution in Integrated Circuit Fabrication Technology and the Art of Device Miniaturization Use of Silicon as a Semiconductor Silicon Devices for Boolean Applications Integration of Silicon Devices and the Art of Circuit Miniaturization MOS and CMOS Devices for Digital Applications LSI, VLSI, and ULSI Circuits and Applications Silicon for MEMS Applications Summary References Silicon: The Key Material for Integrated Circuit Fabrication Technology Introduction Preparation of Raw Silicon Material Metallurgical-Grade Silicon Purification of Metallurgical-Grade Silicon Ultra-High Pure Silicon for Electronics Application Polycrystalline Silicon Feed for Crystal Growth Summary References Importance of Single Crystals for Integrated Circuit Fabrication Introduction Crystal Structures Different Crystal Structures in Nature Cubic Structures Diamond Crystal Structure Silicon Crystal Structure Silicon Crystals and Atomic Packing Factors Crystal Order and Perfection Crystal Orientations and Planes Influence of Dopants and Impurities in Silicon Crystals Summary References Different Techniques for Growing Single-Crystal Silicon Introduction Bridgman Crystal Growth Technique Czochralski Crystal Growth/Pulling Technique Crucible Choice for Molten Silicon Chamber Temperature Profile Seed Selection for Crystal Pulling Environmental and Ambient Control in the Crystal Chamber Crystal Pull Rate and Seed/Crucible Rotation Dopant Addition for Growing Doped Crystals Methods for Continuous Czochralski Crystal Growth Impurity Segregation between Liquid and Grown Silicon Crystals Crystal Growth Striations Use of a Magnetic Field in the Czochralski Growth Technique Large-Area Silicon Crystals for VLSI and ULSI Applications Post-Growth Thermal Gradient and Crystal Cooling after Pull-Out Float-Zone Crystal Growth Technique Seed Selection Environment and Chamber Ambient Control Heating Mechanisms and RF Coil Shape Crystal Growth Rate and Seed Rotation Dopant Distribution in Growing Crystals Impurity Segregation between Liquid and Grown Silicon Crystals Use of Magnetic Field for Float-Zone Growth Large Area Silicon Crystals and Limitations of Shape and Size Thermal Gradient and Post-Growth Crystal Cooling Zone Refining of Single-Crystal Silicon Other Silicon Crystalline Structures and Growth Techniques Silicon Ribbons Silicon Sheets Silicon Whiskers and Fibers Silicon in Circular and Spherical Shapes Silicon Hollow Tubes Casting of Polycrystalline Silicon for Photovoltaic Applications Summary References From Silicon Ingots to Silicon Wafers Introduction Radial Resistivity Measurements Boule Formation, Identification of Crystal Orientation, and Flats Ingot Slicing Mechanical Lapping of Wafer Slices Edge Profiling of Slices Chemical Etching and Mechanical Damage Removal Chemimechanical Polishing for Planar Wafers Surface Roughness and Overall Wafer Topography Megasonic Cleaning Final Cleaning and Inspection Summary References Evaluation of Silicon Wafers Introduction Acoustic Laser Probing Technique Atomic-Force Microscope Studies on Surfaces Auger Electron Spectroscopic Studies Chemical Staining and Etching Techniques Contactless Characterization Deep-Level Transient Spectroscopy Defect Decoration by Metals Electron Beam and High-Energy Electron Diffraction Studies Flame Emission Spectrometry Four-Point Probe Technique for Resistivity Measurement and Mapping Fourier Transform Infrared Spectroscopy Measurements for Impurity Identification Gas Fusion Analysis Hall Mobility Mass Spectra Analysis Minority Carrier Diffusion Length/Lifetime/Surface Photovoltage Optical Methods for Impurity Evaluation Photoluminescence Method for Determining Impurity Concentrations Gamma-Ray Diffractometry Scanning Electron Microscopy for Defect Analysis Scanning Optical Microscope Secondary Ion Mass Spectrometer for Impurity Distribution Spreading Resistance and Two-Point Probe Measurement Technique Stress Measurements Transmission Electron Microscopy van der Pauw Resistivity Measurement Technique for Irregular-Shaped Wafers X-Ray Technique for Crystal Perfection and Dislocation Density Summary References Resistivity and Impurity Concentration Mapping of Silicon Wafers Introduction Electrically Active and Inactive Impurities Surface Mapping and Concentration Contours Surface Roughness Mapping on a Complete Wafer Summary References Impurities in Silicon Wafers Effect of Intentional and Unintentional Impurities and Their Influence on Silicon Devices Intentional Dopant Impurities in Silicon Wafers Aluminum Antimony Arsenic Boron Gallium Phosphorus Unintentional Dopant Impurities in Silicon Wafers Carbon Chromium Copper Germanium Gold Helium Hydrogen Iron Nickel Nitrogen Oxygen Tin Other Metallic Impurities Summary References Defects in Silicon Wafers Introduction Impact of Defects in Silicon Devices and Structures Point Defects and Vacancies Line Defects Bulk Defects and Voids Dislocations and Screw Dislocations Swirl Defects Stacking Faults Precipitations Surface Pits/Crystal-Originated Particles Grown Vacancies and Defects Thermal Donors Slips, Cracks, and Shape Irregularities Stress, Bowing, and Warpage Summary References Silicon Wafer Preparation for VLSI and ULSI Processing Introduction Purity of Chemicals Used for Silicon Processing Degreasing of Silicon Wafers Removal of Metallic and Other Impurities Gettering of Metallic Impurities Denuding of Silicon Wafers Neutron Irradiation Argon Annealing of Wafers Hydrogen Annealing of Wafers Final Cleaning, Rinsing, and Wafer Drying Summary References Packing of Silicon Wafers Packing of Fully Processed Blank Silicon Wafers Storage of Wafers and Control of Particulate Contamination Storage of Wafers and Control of Particulate Contamination with Process-Bound Wafers Summary References Index

Method of manufacturing a semiconductor device and device manufactured according to the method

Abstract: A method of manufacturing a metal silicide pattern with respect to which two electrode zones are to be provided in a self-registering manner. According to the invention the pattern is provided in the form of a layer of polycrystalline silicon and, by selective oxidation and masking, only the upper surface of the pattern is exposed to the silicide formation so that passivation problems and short circuit are avoided. The use of silicides which cannot withstand high temperatures is also possible.

Grain‐Boundary Viscosity of Polycrystalline Silicon Carbides

Abstract: Internal friction experiments were conducted on three SiC polycrystalline materials with different microstructural characteristics. Characterizations of grain-boundary structures were performed by high-resolution electron microscopy (HREM). Observations revealed a common glass-film structure at grain boundaries of two SiC materials, which contained different amounts of SiO2 glass. Additional segregation of residual graphite and SiO2 glass was found at triple pockets, whose size was strongly dependent on the amount of SiO2 in the material. The grain boundaries of a third material, processed with B and C addition, were typically directly bonded without any residual glass phase. Internal friction data of the three SiC materials were collected up to similar/congruent2200°C. The damping curves as a function of temperature of the SiO2-bonded materials revealed the presence of a relaxation peak, arising from grain-boundary sliding, superimposed on an exponential-like background. In the directly bonded SiC material, only the exponential background could be detected. The absence of a relaxation peak was related to the glass-free grain-boundary structure of this polycrystal, which inhibited sliding. Frequency-shift analysis of the internal friction peak in the SiO2-containing materials enabled the determination of the intergranular film viscosity as a function of temperature.

Rapid thermal chemical vapor deposition of germanium on silicon and silicon dioxide and new applications of Ge in ULSI technologies

Abstract: In this study, low pressure chemical vapor deposition of pure germanium on silicon and silicon dioxide has been considered for new applications in future ultra large scale integration (ULSI) technologies. Germanium depositions were performed in a lamp heated cold-wall rapid thermal processor using thermal decomposition of GeH4. It is shown that Ge deposition on Si can be characterized by two different regions: a) at temperatures below approximately 450° C, the deposition is controlled by the rate of surface reactions resulting in an activation energy of 41.7 kcal/mole. b) Above this temperature, mass transport effects become dominant. The deposition rate at the transition temperature is approximately 800 A/min. It is shown that Ge deposition on SiO2 does not occur, even at temperatures as high as 600° C, resulting in a highly selective deposition process. Selectivity, combined with low deposition temperature makes the process very attractive for a number of applications. In this work, it is shown for the first time that selective Ge deposition can be used to eliminate silicon consumption below the gate level during the silicidation of the shallow source and drain junctions of deep submicron MOSFETs. In addition, a new in situ technique has been developed which allows polycrystalline germanium (poly-Ge) deposition on SiO2. In this work poly-Ge has been considered as a low temperature alternative to polycrystalline silicon (poly-Si) in the formation of gate electrodes in single-wafer manufacturing where low-thermal budget processes are most desirable.