Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Manufacturing method for a semiconductor on insulator type substrate for radiofrequency applications

Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radiofrequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate (1) with an electrical resistivity of more than 500 Ohm. cm, (b) formation of a polycrystalline silicon layer (4) on said substrate (1), said method comprising a step between steps a) and b) to form a dielectric material layer (5), different from a native oxide layer, on the substrate (1), between 0.5 and 10 nm thick.

New challenges in thin film transistor (TFT) research

Abstract: This paper addresses the current trends in research and development for: (1) Thin film transistors (TFTs) on plastic substrates, (2) low-temperature poly-silicon (LTPS) for the pixel TFTs and for row and column drivers on glass, (3) addressing of organic light emitting diodes by silicon TFTs. For these advanced applications of TFTs the relevant issues are: (i) higher electron mobility, (ii) stability, and (iii) defect free, uniform deposition of thin silicon films and gate dielectrics at a high deposition rate (reduced cost). At Utrecht University, we are investigating hot wire (catalytic) chemical vapor deposition (CVD) as a deposition technique for novel TFTs that have a high potential to meet the above mentioned requirements. Bottom gate, inverted staggered TFTs with hot wire CVD (HWCVD) silicon films have been made with an electron mobility of 1.5 cm 2 / V s , and with field effect characteristics that are completely stable under operating conditions. Top gate, coplanar TFTs with polycrystalline silicon (poly-Si) films have been made, which showed a mobility of 4.7 cm 2 / V s . This has been obtained without any post treatment, and the hot wire technology can thus avoid expensive, time-consuming steps such as laser recrystallization as currently used in the production of the latest poly-Si lap top displays. HWCVD is also suitable for the deposition of SiNx:H gate dielectrics. TFTs with a hot wire silicon nitride gate dielectric have been deposited.

Dielectrically isolated semiconductor devices

Abstract: The invention is a method of fabricating dielectrically isolated semiconductor regions adapted for the construction of an integrated circuit on an epitaxial wafer wherein the epitaxial wafer has a first layer of monocrystalline n+ type silicon of a predetermined thickness and a second layer of epitaxially deposited n-type silicon which is substantially thinner than the first layer. A layer of silicon dioxide is grown on the back side of the first layer of the wafer and a layer of polycrystalline silicon is deposited onto the silicon dioxide layer. An aluminum oxide mask is formed defining a plurality of grooves around active semiconductor regions within the n-type silicon layer. The grooves are formed by a sputter etching process. Silicon dioxide is thermally grown within each of the grooves exposed by the sputter etching process to dielectrically isolate the active semiconductor regions after which semiconductor devices may be formed in each of the active semiconductor regions.

Method of manufacturing a buried plate type DRAM having a widened trench structure

Abstract: A trench of a buried plate type DRAM has a bottom portion wider than an opening portion. A silicon oxide film is formed on an upper portion of the side wall of the trench. An N-type impurity diffusion region is formed around the bottom portion of the trench. Impurity diffusion regions of adjacent trenches are integrally connected with each other as one portion. A first polycrystalline silicon layer is formed on the impurity diffusion region in the trench and the silicon oxide film. The polycrystalline silicon layer is coated with a laminated film consisting of a silicon nitride film and a silicon oxide film. The trench is filled with a second polycrystalline silicon layer covering the laminated film. The impurity diffusion region serves as a plate diffusion region of a capacitor, the first polycrystalline silicon layer serves as a plate electrode, the laminated film serves as a capacitor insulating film, and the second polycrystalline silicon layer serves as a storage node electrode. The capacitor is formed in the trench.

Thermal Oxidation of Phosphorus‐Doped Polycrystalline Silicon in Wet Oxygen

Abstract: Oxidation characteristics of heavily phosphorus‐doped polycrystalline silicon films and single crystal silicon substrates are investigated in a wet oxygen ambient over the temperature range 700°–850°C based on the linear‐parabolic rate law. Polysilicon, undoped or uniformly doped with phosphorus of by diffusion drive‐in or ion implantation, is studied in comparison with lightly doped or heavily doped (100), (110), and (111) faces of silicon substrates. Phosphorus concentrations greater than cause a significant increase in oxidation rates. Above , however, oxidation rates tend to become saturated. A very rapid oxidation in the initial stage of oxidation is observed. This initial oxide does not fit the linear‐parabolic rate law. The resistivity of the phosphorus‐doped polysilicon is minimized at for a phosphorus concentration of around . The initial resistivity remains almost constant after reduction of the polysilicon thickness by oxidation. In addition, no evidence of enhanced oxidation along the grain boundaries is observed.