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Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.


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Patent
11 Jun 1990
TL;DR: In this article, the problem of obtaining a good contact between a semiconductor layer and electrode wiring was addressed by separating a source drain area from a gate electrode after simultaneously forming the source-drain area and gate electrode and connecting the source drain with electrode wiring through a polycrystalline silicon film which is reduced in resistance.
Abstract: PURPOSE:To obtain a good contact between a semiconductor layer and electrode wiring even when the thickness of the semiconductor layer is reduced by separating a source-drain area from a gate electrode after simultaneously forming the source-drain area and gate electrode and connecting the source-drain area with electrode wiring through a polycrystalline silicon film which is reduced in resistance. CONSTITUTION:An electrode contacting member 9 which is separated from a gate electrode 5 and produced from the same polycrystalline silicon film as that used for the gate electrode 5 by reducing the resistance by patterning is provided in a source-drain area 8 and, at the same time, an insulating film 3 formed on a semiconductor layer 2 is patterned so that the film 3 can be left below the gate electrode 5 only. Moreover, electrode wiring 7 is brought into contact with the source-drain area 8 through the electrode contacting member. 9. Therefore, a good contact can be obtained with a wiring material even when the thickness of the semiconductor layer 2 is reduced.

50 citations

Journal ArticleDOI
TL;DR: In this article, a tensile tester for thin polycrystalline silicon (poly-Si) thin films is presented, which has been constructed in a scanning electron microscope (SEM) chamber.
Abstract: In this paper, a new tensile tester for thin films is presented. This tensile tester has a grip that fixes a thin film specimen using electrostatic force. The tester was constructed in a scanning electron microscope (SEM) chamber. Using this tester, the tensile strengths of polycrystalline silicon (poly-Si) thin films have been measured. The tested part of the specimen is 30-300μm long, 5μm wide and 2μm thick. The fracture of the poly-Si thin film was brittle. The mean tensile strength was 2.0-2.6GPa, depending on the length of the tested part. The size of the critical flaw that initiates fracture of the poly-Si thin film is 28-47nm, rather small than the grain size of the poly-Si thin film.

50 citations

Patent
Sridhar K. Iya1
30 Jul 1985
TL;DR: An improved heated fluidized bed reactor and method for the production of high purity polycrystalline silicon by silane pyrolysis was proposed in this paper, where silicon seed particles are heated in an upper heating zone of the reactor and mixed with particles in a lower zone, in which zone a silane-containing gas stream, having passed through a lower cooled gas distribution zone not conducive to silane Pyrolysis, contacts the heated seed particles whereon the silane is heterogeneously reduced to silicon.
Abstract: An improved heated fluidized bed reactor and method for the production of high purity polycrystalline silicon by silane pyrolysis wherein silicon seed particles are heated in an upper heating zone of the reactor and admixed with particles in a lower zone, in which zone a silane-containing gas stream, having passed through a lower cooled gas distribution zone not conducive to silane pyrolysis, contacts the heated seed particles whereon the silane is heterogeneously reduced to silicon.

50 citations

Patent
20 Dec 1988
TL;DR: In this paper, the authors proposed a method to stabilize a transistor in characteristics by a method wherein a first gate electrode is formed, a second N.type impurity layer is formed by diffusion on the entirety or a prescribed region of a semiconductor substrate, and, in a second gate channel region, unnecessary portions of the second N-type impurate layer and the semiconductor substrategies are subjected to etching.
Abstract: PURPOSE:To stabilize a transistor in characteristics by a method wherein a first gate electrode is formed, a second N.type impurity layer is formed by diffusion on the entirety or a prescribed region of a semiconductor substrate, and, in a second gate channel region, unnecessary portions of the second N-type impurity layer and the semiconductor substrate are subjected to etching. CONSTITUTION:A first N-type diffusion layer 3 is formed on a silicon substrate 1. Next, a first gate oxide film 4 is formed and, thereon, a first polycrystalline silicon 5 is formed. The first polycrystalline silicon 5 and the first gate oxide film 4 are patterned, which is accomplished according to the geometry of a second resist mask 6. An N-type impurity is diffused into the primary surface of the silicon substrate 1, and then a second N-type diffusion layer 7 is formed. A process follows wherein a third resist mask 8 is formed and the silicon substrate 1 is etched through the second and third resist masks 6 and 8. In this process, etching is so accomplished as to remove only the portions of the first N-type diffusion layer 3 and the second N-type diffusion layer 7 located not under the second and third resist masks 6 and 8. This method realizes a transistor with its characteristics stabilized.

50 citations

Patent
21 Jan 1987
TL;DR: In this article, the authors proposed to improve the efficiency and accuracy of information writing by deeply inverting the separating region of a source region and a floating gate at writing time in an EPROM, thereby preventing between the source and the drain from punching through.
Abstract: PURPOSE:To improve the efficiency and the accuracy of information writing by deeply inverting the separating region of a source region and a floating gate at writing time in an EPROM, thereby preventing between the source and the drain from punching through. CONSTITUTION:An EPROM cell has an N type drain region 4 and an N type source region 5 in an element forming region separated and presented at a P type silicon substrate 1 by a field SiO2 film 2 and a P-type channel stopper 14. A floating gate 7 made of polycrystalline silicon layer is arranged, and a control gate 9 made of polycrystalline silicon layer is extended and disposed on the region 5 and the separating portion OFS. A deep inverted layer INV is formed on the substrate of the separating portion OFS by a selective voltage applied to the gate 9 at writing time, the layer INV suppresses the extension of a depletion layer DEP, thereby effectively writing without punch- through between the source and the drain.

50 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202343
2022130
2021122
2020313
2019498
2018534