Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors

Abstract: A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the oxide-silicon interface traps can be extracted. Potential and carrier density are also extracted. From the potential, carrier density, and current–voltage characteristic, the grain boundary traps can be extracted by considering the potential barrier at the grain boundary. Since these trap states are sequentially extracted, any shape of energy distribution of the trap states can be extracted. The correctness of this extraction technique is confirmed by comparison with two-dimensional device simulation.

DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance

Abstract: A DRAM cell having enhanced capacitance attributable to the use of a textured polycrystalline silicon storage-node capacitor plate (65). The present invention is particularly applicable to DRAM cells which employ a stacked-capacitor design, as such designs generally a conductively-doped polycrystalline silicon layer as the storage-node, or lower, capacitor plate. A poly texturization process imparts a three-dimensional texturized character to the upper surface of a first polysilicon layer (57). Texturization of this layer is accomplished by subjecting it to a wet oxidation step. Since oxidation at the crystal grain boundaries on the surface of first poly layer (57) proceeds more rapidly than elsewhere, the surface becomes bumpy. When maximum texturization has been achieved, the overlying oxide (59) is removed from first poly layer (57) during a wet etch step. With texturization complete, first poly layer (57) is patterned to form a storage node plate (65). A thin (70-100 angstroms thick) silicon nitride layer (67) is deposited on top of storage node plate (65), followed by the deposition of a second poly layer (69), which, after patterning, functions as the capacitor field plate. Since the nitride layer (67) is thin in comparison to the bumps on the surface of the storage-node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased approximately thirty percent using a storage-node plate so texturized.

Process for manufacturing a semiconductor device

Abstract: A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type. Sidewall spacers are formed at the edges of the gate electrodes by anisotropically etching a sidewall spacer forming material. Because of the differential thickness of the gate electrode structures, the spacers at the edges of the N-type doped gate electrodes will be of a different thickness than are the sidewall spacers at the edges of the silicon gates not having the N-type doping. The sidewall spacers of different width are, in turn, used as a dopant mask for the formation of doped regions within the surface of the semiconductor substrate. The disclosed process allows independent doping of the polycrystalline silicon and the semiconductor substrate. A high doping concentration in the polycrystalline silicon helps to minimize the diffusing of dopant through a metal silicide layer formed on the polycrystalline silicon.

Time‐dependent positive charge generation in very thin silicon oxide dielectrics

Abstract: We have studied the rate at which positive charge is generated starting near the oxide‐silicon interface when electrons are injected from the gate through the very thin oxide layer in metal‐oxide‐(p)silicon tunnel diodes. By varying the oxide thickness, we find that the charging rate is not strongly controlled by the flux of tunneling electrons over a five order of magnitude range in current density. This implies that if the tunneling electrons do participate, then the charge generation in these oxides is at least a two‐step process. A comparison of charge generation in aluminum and polycrystalline silicon gate devices suggests that the process does not involve aluminum‐related defects. Measurements of the charging rate versus temperature, T, show that it is weakly dependent on T below 150–200 K and apparently thermally activated above this temperature range.