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Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.


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Patent
21 Jan 1991
TL;DR: In this paper, the surface of a semiconductor substrate consisting of some one of laminated wafers is shaved off so as to leave a necessary thickness at the bonding part of the substrate with an intrinsic base and a single crystal is buried in a hole formed by anisotropic etching.
Abstract: PURPOSE:To lessen the number of processes by a method wherein the surface of a semiconductor substrate consisting of some one of laminated wafers is shaved off so as to leave a necessary thickness at the bonding part of the substrate with an intrinsic base and a single crystal is buried in a hole formed by anisotropic etching. CONSTITUTION:A P-type single crystal substrate 3 is prepared, oxide layers 2 and 4 are arranged so as to come into contact with each other and an electrostatic contact bonding is performed. Then, a hole, which passes through the layers 2 and 4 and reaches the P-type Si substrate 3, is opened by anisotropic etching and this hole is filled with a single crystal Si film 5 by an epitaxial growth. The silicon film 5 deposited on a place other than this hole is removed. An emitter window is opened in an oxide layer 11 by anisotropic etching. An oxide layer 21 is etched to form an emitter diffusion window. A polycrystalline silicon film 22 is deposited in the vicinity of this window, an annealing is performed to form a P-N-P transistor and an N-type emitter diffused region 9, a P-type diffused region 10 and a collector contact compensation diffused region 8 are simultaneously formed. Thereby, a bipolar transistor structure can be manufactured in a process of the number of few processes.

47 citations

Journal ArticleDOI
TL;DR: In this paper, the characterization of polycrystalline silicon MOS transistors and its film properties is studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena.
Abstract: The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films

47 citations

Patent
22 Aug 2000
TL;DR: In this paper, the root-mean-square (RMS) surface roughness of polycrystalline waveguides was achieved by annealing amorphous silicon (a-Si) to form a poly-Si waveguide.
Abstract: Methods of forming polycrystalline semiconductor waveguides include the steps of forming a first cladding layer (e.g., SiO2) on a substrate (e.g., silicon) and then forming a polycrystalline semiconductor layer (e.g., poly-Si) on the first cladding layer using a direct deposition technique or by annealing amorphous silicon (a-Si) to form a polycrystalline layer, for example. The deposited polycrystalline semiconductor layer can then be polished at a face thereof to have a root-mean-square (RMS) surface roughness of less than about 6 nm so that waveguides patterned therefrom have loss ratings of better than 35 dB/cm. The polished polycrystalline semiconductor layer is then preferably etched in a plasma to form a plurality of polycrystalline strips. A second cladding layer is then formed on the polycrystalline strips to form a plurality of polycrystalline waveguides which provide relatively low-loss paths for optical communication between one or more optoelectronic devices coupled thereto. The annealed amorphous silicon layer or deposited polycrystalline layer can also be hydrogenated by exposing the second cladding layer to a hydrogen containing plasma at a temperature and pressure of about 350 DEG C. and 0.16 mTorr, respectively, and for a duration in a range between about 30 and 60 minutes. This further improves the loss ratings of the waveguides to about 15 dB/cm or less.

47 citations

Patent
30 Jan 1992
TL;DR: In this article, a thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of less than 2500 Å and active matrix assemblies including thin film transistors provide improved thin-type displays.
Abstract: Thin film transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of less than 2500 Å and active matrix assemblies including thin film transistors provide improved thin-type displays.

47 citations

Journal ArticleDOI
TL;DR: In this paper, a double-layer polycrystalline-silicon (SIPOS) film is employed as a replacement of a thick silicon dioxide layer in C/MOS-IC's of channel-stopperless structure and exhibits excellent field-passivating properties.
Abstract: A semi-insulating polycrystalline-silicon (SIPOS) film doped with oxygen atoms is deposited on the surface of silicon substrates by a chemical vapor reaction of silane and nitrous oxide in nitrogen ambient, and has been studied for the surface passivation of MOS-IC's, in particular, C/MOS-IC's of channel-stopperless structure. SIPOS films are semi-insulating and intrinsically neutral. A double-layer system consisting of 3000 A SIPOS and 6000 A SiO2 films is employed as a replacement of a thick silicon dioxide layer in C/MOS-IC's of channel-stopperless structure and exhibits excellent field-passivating properties, namely, a small drain-source leakage current, a high drain breakdown voltage, and a high parasitic threshold voltage. Furthermore, the silicon surface passivated by SIPOS films shows high stability under a severe bias-temperature stress. It is concluded that C/MOS-IC's passivated by SIPOS films are not required to have a channelstopper diffusion region and can be operated at high applied voltages, which leads to higher integrating density and higher reliability.

47 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202343
2022130
2021122
2020313
2019498
2018534