Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations

Abstract: A comparison is made between the results of high‐resolution electron microscope observations and the electrical characteristics of polycrystalline silicon emitter bipolar transistors. Devices are fabricated with and without a deliberately grown interfacial oxide layer, and the thermal stability of this oxide layer is investigated by carrying out a preanneal at temperatures between 800 and 1100 °C after polysilicon deposition, but prior to emitter implant and 900 °C drive‐in. The electron microscope observations show that the deliberately grown interfacial oxide is of uniform thickness ∼14 A, but breaks up when annealed at ∼950 °C and above, with ‘‘balling‐up’’ occurring at ∼1100 °C. This correlates with a transistor gain that decreases from ∼1400 to ∼40. The electron microscopy also shows that a thin interfacial oxide layer is present even when not deliberately grown. This oxide breaks up when annealed at ∼900 °C and above, with ‘‘balling‐up’’ occurring at ∼1000 °C. This correlates with a transistor gain that decreases from ∼240 to ∼50. Calculations of the effect that such interfacial oxide layers will have on the characteristics of polysilicon emitter bipolar transistors are made, and these predictions correlate well with the measured characteristics.

Method for forming a thin, high quality buffer layer in a field effect transistor and related structure

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

Abstract: In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

The Effect of Low Pressure on the Structure of LPCVD Polycrystalline Silicon Films

Abstract: Structure and crystal growth of undoped silicon films prepared by low pressure chemical vapor deposition (LPCVD) have been investigated by x‐ray diffraction, and transmission and scanning electron microscopy. We show that for films deposited in silane partial‐pressure range and temperature range , the pressure is a determining factor for crystallite size, texture, and surface roughness. At a fixed temperature, the crystallite size decreases when the pressure increases. At very low pressures the films have a random orientation. At intermediate pressures the films are characterized by a dominant texture and at high pressure, by a strong preferred orientation. The surface roughness is closely related to the preferred orientation.

Process for Polycrystalline film silicon growth

Abstract: A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide The deposition occurs beneath the vapor barrier One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities The process is capable of repetition without the need to reset the deposition zone conditions