Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Abstract: Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralargescale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

Silicide formation in thin cosputtered (tantalum + silicon) films on polycrystalline silicon and SiO2

Abstract: Formation of the silicides of titanium has been investigated by cosputtering titanium and silicon on polycrystalline silicon and oxidized silicon wafers. Alloys with as‐deposited Si/Ti atomic ratios of 0.5–8 were sintered in vacuum or hydrogen ambient in the temperature range 400–1000 °C. The Ti‐Si interaction in such films was studied by the use of sheet resistance, x‐ray diffraction, and stress measurements. It was found that in cases of silicon deficient alloys (e.g., the case of alloys sputtered on oxide with Si/Ti ratio <2) intermetallics Ti5Si3 and TiSi were formed. These intermetallics were stable up to 900 °C. In the presence of polycrystalline silicon and for alloys with Si/Ti ratio ?2, the only intermetallic formed was TiSi2. TiSi2 was responsible for very low resistivity (as low as ∼25 μΩcm) in the films. The volume change associated with silicide formation led to high tensile stresses in the films. It is suggested that in cosputtered films metallurgical interaction occurs locally which leads t...

Photonic network-on-chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessors

Abstract: Integrated photonics has been slated as a revolutionary technology with the potential to mitigate the many challenges associated with on- and off-chip electrical interconnection networks. To date, all proposed chip-scale photonic interconnects have been based on the crystalline silicon platform for CMOS-compatible fabrication. However, maintaining CMOS compatibility does not preclude the use of other CMOS-compatible silicon materials such as silicon nitride and polycrystalline silicon. In this work, we investigate utilizing devices based on these deposited materials to design photonic networks with multiple layers of photonic devices. We apply rigorous device optimization and insertion loss analysis on various network architectures, demonstrating that multilayer photonic networks can exhibit dramatically lower total insertion loss, enabling unprecedented bandwidth scalability. We show that significant improvements in waveguide propagation and waveguide crossing insertion losses resulting from using these materials enables the realization of topologies that were previously not feasible using only the single-layer crystalline silicon approaches.

Irreversible semiconductor switching element and semiconductor memory device utilizing the same

Abstract: A semiconductor switching element comprised by a high resistivity polycrystalline silicon resistor whose resistance irreversibly decreases to a small value at a threshold voltage upon the voltage across the resistor reaching the threshold voltage. A semiconductor memory device is constituted by using the switching element as a memory cell and a semiconductor gate element for controlling the current flowing through the semiconductor switching element.

Anisotropic plasma etching of polysilicon

Abstract: Plasma etching of polycrystalline silicon films for fabrication of silicon gate MOS integrated circuits has been studied with emphasis on fine‐line devices. CF4–O2 plasmas, commonly used for etching silicon, are unacceptable for very fine features because the etching is isotropic and load dependent. This results in substantial undercutting and insufficient dimensional control. Several alternative gases were investigated in a parallel–plate reactor. CF3Cl and a 70% CF3Br–30% He mixture were found to provide selectivities of 30:1 and 16:1, respectively, over thermal SiO2, freedom from loading effects and a large vertical to lateral etch rate anisotropy which minimizes undercutting. Extensive measurements of etch rate and edge profile as a function of gas composition were made for C2F6–Cl2 plasmas. Fully anisotropic etching (zero lateral etch rate) was observed at low Cl2 concentrations with a selectivity ≳6:1 over thermal SiO2 when using conventional photoresist masks. The vertical and lateral etch rates an...