Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Progress in Laser-Crystallized Thin-Film Polycrystalline Silicon Solar Cells: Intermediate Layers, Light Trapping, and Metallization

Abstract: Diode laser crystallization of thin silicon films on the glass has been used to form polycrystalline silicon layers for solar cells. Properties of an intermediate layer stack of sputtered SiOx/SiNx/SiOx between the glass and the silicon have been improved by reactively sputtering the SiNx layer, which result in enhanced optical and electrical performance. Light trapping is further enhanced by texturing the rear surface of the silicon prior to metallization. An initial efficiency of 11.7% with VOC of 585 mV has been achieved using this technique, which are the highest values reported for poly-Si solar cells on glass substrates. Cells suffer a short term, recoverable degradation of VOC, and fill factor. The magnitude of the degradation is reduced via the repeated thermal treatment. A selective p+ metallization scheme has been developed which eliminates the degradation altogether.

Evidence for surface asperity mechanism of conductivity in oxide grown on polycrystalline silicon

Abstract: High conductivity observed in oxides grown on polycrystalline silicon has been previously speculated as being due to asperities on the silicon surface, which enhance the oxide field. Direct evidence of these asperities is shown here in SEM micrographs. The presence of the asperities is strongly correlated with the oxide conductivity (as controlled by the oxidation temperature).

Optical transmission losses in polycrystalline silicon strip waveguides: effects of waveguide dimensions, thermal treatment, hydrogen passivation, and wavelength

Abstract: Signal propagation delays dominate over gate delays in the ever-shrinking ultra large scale integrated (ULSI) circuits. Consequently, silicon-based monolithic optoelectronic circuits (SMOE) with their light speed signal propagation can provide unique advantages for future generations of microprocessors. For such SMOE circuits, we need optical interconnects compatible with silicon technology. Strip waveguides consisting of polycrystalline silicon (polySi) clad with SiO2 offer excellent optical confinement and ease of fabrication that are ideal for such interconnect applications. One major challenge with using this material system, however, is its insertion loss. In this paper we provide techniques for minimizing optical transmission losses in polySi strip waveguides. Our previous work using polySi strip waveguides, showed an optical transmission loss of 15 dB/cm at λ=1.55 µm, which is a communication wavelength of choice in optical fibers because it represents an absorption minimum. Similar measurements in crystalline silicon strip waveguides1 yielded transmission losses of less than 1 dB/cm. Hitherto, in decreasing loss from 77 dB/cm to 15 dB/cm, we had minimized loss from surface scattering by improving the film surface morphology, and decreased bulk absorption with hydrogen passivation. In this paper we report a further reduction in the residual bulk loss from 15 dB/cm to 9 dB/cm. By experimenting with different waveguide core dimensions, we find that the contribution of bulk loss towards net transmission loss decreases with waveguide core thickness. Additionally, high temperature treatment provides strain relief in the polySi, decreasing transmission loss. Annealing in an oxygen ambient is not recommended because it always increases transmission loss. Hydrogen passivation improves transmission, attributable to passivation of light-absorbing dangling bond defect sites present at polySi grain boundaries. Together, these methods have resulted in the lowest measured loss value of 9 dB/cm at λ=1.55 µm. Since integrated SiGe and Ge photodetectors are more efficient at shorter wavelengths like λ=1.32 µm, transmission loss is also measured at λ=1.32 µm. Losses at the two wavelengths (1.32 µm and 1.55 µm) are similar when defects and stress in the waveguides are minimized.

Dram cell and method

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

Grain boundary states and the characteristics of lateral polysilicon diodes

Abstract: In lateral n+p−p+ diodes made in LPCVD polycrystalline silicon films, the energy distribution of the traps at the grain boundaries is found to be U shaped. They have a density of about 1012 cm−2 and a capture cross section of about 10−16 cm2. The forward current of the diodes is ascribed to recombination, the reverse current to field-enhanced generation via these traps.