Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Structure of As‐Deposited LPCVD Silicon Films at Low Deposition Temperatures and Pressures

Abstract: In this work we studied the effect of the deposition temperature, total pressure, source gas dilution, and deposition rate on the structure of the as‐deposited silicon films. Depositions were performed by low pressure chemical vapor deposition (LPCVD) in the temperature range of 530 to 600°C and in the pressure range of 2 to 300 mTorr. For a fixed deposition temperature a phase transition from polycrystalline to amorphous silicon was shown to occur when the deposition rate exceeded a critical value. The critical value for the deposition rate was found to depend only upon the deposition temperature and to decrease as the temperature was decreased. By controlling the rate, as‐deposited polycrystalline silicon was obtained by conventional LPCVD at temperatues as low as 530°C. A relationship between the deposition rate and the partial pressure of the source gas was established via a kinetic model for the decomposition of silane and used to provide a simple model for the dependence of the structure of the as‐deposited silicon films upon the deposition parameters. This model was subsequently used to provide guidelines for both the expected structure of the as‐deposited films and the grain size of the as‐deposited polycrystalline silicon films over an extensive range of deposition conditions.

Electrowinning of Silicon from K 2SiF6 ‐ Molten Fluoride Systems

Abstract: The electrowinning of silicon from solutions of in fluoride melts at 745°C has been achieved. Electrolysis close to the deposition potential gave dense, coherent, and well‐adherent deposits. Up to 3 mm thick films were grown using a concentration of 4–6 m/o. The polycrystalline silicon has a columnar structure with grain size up to 100 μm. The morphology of the electrodeposited silicon onto silver substrates and its dependence on the deposition parameters is discussed. The purity of the deposits is substantially higher than that previously reported for electrodeposited silicon.

Method of gettering using backside polycrystalline silicon

Abstract: An integrated circuit structure and method for manufacturing same which provides for gettering with a backside layer of polycrystalline silicon. The gettering of unwanted impurities from the integrated circuits involves the deposition of a polycrystalline silicon film on a semiconductor wafer prior to any or some high temperature processing steps. The semiconductor body is then subjected to the normal semiconductor processing steps to form semiconductor devices on the surface opposite to the surface having the polycrystalline silicon layer. During these high temperature processing steps, unwanted impurities such as copper, iron, nickel, sodium and potassium ions move toward and into the polycrystalline silicon layer and thereby away from the semiconductor devices. This produces improved yield in the integrated circuit process.

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Abstract: The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced