Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Method for manufacturing a liquid crystal display substrate

Abstract: An amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the amorphous silicon film is changed to a plurality of polycrystalline silicon regions which are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses each having the same dimensions as those of the island region onto the amorphous silicon film, using a laser beam irradiating section. Switching elements including the island regions as semiconductor regions are formed by etching and film-forming process to constitute a driving circuit section. The section is divided to gate driving circuit sections and source driving circuit sections for driving thin film transistors formed in a pixel region.

The effects of dopants on surface‐energy‐driven secondary grain growth in silicon films

Abstract: The effects of phosphorus, arsenic, and boron on surface‐energy‐driven secondary grain growth (SEDSGG) in thin polycrystalline silicon films have been investigated. At concentrations at or above 5×1020 cm−3, phosphorus and arsenic were found to markedly enhance SEDSGG while boron had little effect. However, codoping with phosphorous and boron or arsenic and boron lead to compensation (reduction or elimination) of the enhancement effect. The kinetics of SEDSGG were analyzed using transmission electron microscopy. In order to identify electronic as well as segregation effects of dopants on the kinetics of SEDSGG, electron concentrations in the Si films were determined from Hall measurements and dopant segregation was directly measured using scanning transmission electron microscopy and energy‐dispersive x‐ray analysis. Analogous to normal grain growth, dopant‐induced enhancement of SEDSGG can be explained in terms of an increased grain‐boundary atomic mobility due to changes in point‐defect concentrations r...

Theory of conduction in polysilicon: Drift-diffusion approach in crystalline-amorphous-crystalline semiconductor system—Part I: Small signal theory

Abstract: A theory of conduction in polycrystalline silicon is presented. The present approach fundamentally differs from previous theories in its treatment of the grain boundary. This theory regards the grain boundary as amorphous semiconductor in equilibrium contact with crystalline grain. The model explains the electrical properties of polysilicon in terms of the electronic and structural parameters of the material and is in excellent agreement with the experimental data. The formulation is applicable for arbitrary grain size, temperature, doping concentration, and applied voltage. Specifically, the temperature dependence of resistivity is explained in terms of conduction channels inherent in the amorphous grain boundary. Also, this paper explicitly compares the previous emission theories with the present model in terms of voltage partition scheme and I - V predictions.

Fluidized bed reactor with microwave heating system for preparing high-purity polycrystalline silicon

Abstract: An apparatus for preparing high-purity polycrystalline silicon is constructed with a heating applicator, a vertical fluidized bed quartz reactor within the applicator, a microwave generator, microwave guide tubes for conveying microwaves from the microwave generator to the applicator, a reacting gas inlet and outlet, a gas distribution device for distributing reacting gas within the reactor, a silicon seed inlet for introducing silicon seed into the reactor, and an outlet for withdrawing polycrystalline silicon from the reactor. The microwaves provide the heat for the fluidized bed reaction.

Transformational silicon electronics.

Abstract: In today’s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry’s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage ...