Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Metaheuristic Algorithm for Photovoltaic Parameters: Comparative Study and Prediction with a Firefly Algorithm

Abstract: In this paper, a Firefly algorithm is proposed for identification and comparative study of five, seven and eight parameters of a single and double diode solar cell and photovoltaic module under different solar irradiation and temperature. Further, a metaheuristic algorithm is proposed in order to predict the electrical parameters of three different solar cell technologies. The first is a commercial RTC mono-crystalline silicon solar cell with single and double diodes at 33 °C and 1000 W/m2. The second, is a flexible hydrogenated amorphous silicon a-Si:H solar cell single diode. The third is a commercial photovoltaic module (Photowatt-PWP 201) in which 36 polycrystalline silicon cells are connected in series, single diode, at 25 °C and 1000 W/m2 from experimental current-voltage. The proposed constrained objective function is adapted to minimize the absolute errors between experimental and predicted values of voltage and current in two zones. Finally, for performance validation, the parameters obtained through the Firefly algorithm are compared with recent research papers reporting metaheuristic optimization algorithms and analytical methods. The presented results confirm the validity and reliability of the Firefly algorithm in extracting the optimal parameters of the photovoltaic solar cell.

Development and electrical properties of undoped polycrystalline silicon thin film transistors for guest-host LCDs

Abstract: It is demonstrated that it is possible to use TFTs (thin-film transistors) to construct CMOS inverters operating at 40 V In addition, the authors discuss qualitatively and quantitatively the changes which take place in the grain boundary trap density on removal of HCl during gate oxidation and on grain boundary passivation by hydrogenation Quantitative measurements of I/sub DS/ as a function of V/sub G/ show that the removal of HCl during gate oxidation of polysilicon lowers the grain boundary trap density by about one third This is a small but still significant improvement in addition to the reductions by factors of 6 to 9 obtained through hydrogenation The activation energy for source-drain conduction at low values of V/sub G/ was measured to be 055 eV and indicates that conduction is controlled by the supply of carriers from mid-gap grain boundary states The activation energy of dual gated devices is twice that for a single gated structure, since at values of V/sub G/ close to the conduction minimum, both gates equally control conduction >

Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode. This amorphous layer is then implanted with a dopant capable of forming a source/drain region in the underlying silicon substrate by subsequent diffusion of the implanted dopant from the amorphous silicon layer into the substrate. The structure is then annealed to diffuse the dopant from the implanted silicon layer into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to dope the polysilicon. The annealing further serves to cause the amorphous silicon layer to crystalize to polycrystalline silicon (polysilicon). In one embodiment, the polysilicon layer is then nitridized to convert it to a silicon nitride layer which is then patterned to form silicon nitride spacers on the sidewalls of the polysilicon gate electrode to electrically insulate the gate electrode from the source/drain regions. The process may be further modified to also create LDD or HDD source/drain regions in the substrate (depending on the concentration of the dopant), using multiple implants into the same silicon layer or by the sequential use of several silicon layers, each of which is used as an implantation and out-diffusion layer.