Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Abstract: Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration N off in offset-gate regions. Leakage current markedly decreases from 1 × 10-9to 2 × 10-11A at V D = 10 V as N off is varied from 1 × 1018to 1 × 1017cm-3. A maximum ON/OFF current ratio of 108is obtained at 1 × 1017cm-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.

Fabrication methods for high performance lateral bipolar transistors

Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Semi-Insulating Polycrystalline-Silicon (SIPOS) Passivation Technology

Abstract: Semi-insulating polycrystalline-silicon (SIPOS) films have been used as a replacement of a silicon dioxide passivation layer of planar devices. The SIPOS films are chemically vapordeposited polycrystalline-silicon doped with oxygen or nitrogen atoms. The passivation properties of oxygen-doped SIPOS films have been examined as a function of oxygen concentration. The npn and pnp transistors rated at 800 V and 2500 V have been produced by the SIPOS process in planar-like structures with field-limiting rings. The leakage currents of 800 V pnp transistors did not increase even after the chips were exposed to water vapor at 100°C and to sodium contamination at 200°C. Thus, the SIPOS transistors can be packaged in low-cost molded epoxy as well as metal cans. Furthermore, 10 kV SIPOS transistors with multiple rings have been fabricated and their operation has been found to be stable.

Silicon Oxidation Studies: Morphological Aspects of the Oxidation of Polycrystalline Silicon

Abstract: Previous studies have shown that the oxide grown from polycrystalline silicon displays degraded reliability in terms of higher leakage current and premature dielectric breakdown as compared with the oxide grown from single crystal silicon. Present transmission electron microscope studies of the morphology of polycrystalline silicon films and the oxide grown therefrom show several novel features. The polycrystalline silicon becomes rougher after oxidation, the oxide displays thickness undulations which replicate the previous grain boundaries with thinner oxide over grain boundaries, and the oxide forms intergranularly as well as on the free silicon surface. Despite the intergranular oxide formation, the film skin of oxidized polycrystalline silicon does not become significantly more compressive. The surface roughness features of the polycrystalline silicon and oxide and the film stress values are explained by a Si creep mechanism. From these studies some aspects of the reliability of polycrystalline silicon and oxide are understood.

AC Drive type electroluminescent display device

Abstract: The AC drive type electroluminescent display device comprises a combination of an electroluminescent element, a transistor for driving the electroluminescent element, a source of alternating current, a switching transistor ON/OFF--controlling the first mentioned transistor, and a capacitor. The transistor for driving the electroluminescent element comprises a channel region of a first conductivity type and made of polycrystalline silicon with its grain size increased, first and second impurity diffused layers on the opposite sides of the channel region and a gate electrode overlying a predetermined portion of the channel region via a gate insulating film. The gate electrode is made of polycrystalline silicon diffused with an impurity of a second conductivity type. Offset gate regions are formed between the gate electrode and the first and second impurity diffused layers respectively.