Polycrystalline silicon

About: Polycrystalline silicon is a research topic. Over the lifetime, 19554 publications have been published within this topic receiving 198222 citations. The topic is also known as: polysilicon & poly-Si.

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

Abstract: We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950/spl deg/C. The substrates were 0.2-mm thick steel foil coated with 0.5-/spl mu/m thick SiO/sub 2/. We employed silicon crystallization times ranging from 6 h (600/spl deg/C) to 20 s (950/spl deg/C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO/sub 2/ made by thermal oxidation or from deposited SiO/sub 2/. The field-effect mobilities reach 64 cm/sup 2//Vs for electrons and 22 cm/sup 2//Vs for holes. Complementary metal-oxide-silicon (CMOS) circuits were fabricated with self-aligned TFT geometries, and exhibit ring oscillator frequencies of 1 MHz. These results lay the groundwork for polycrystalline silicon circuitry on flexible substrates for large-area electronic backplanes.

Properties of tungsten silicide film on polycrystalline silicon

Abstract: Tungsten silicide on polycrystalline Si becomes increasingly important as interconnections and gate electrodes for metal‐oxide‐semiconductor field‐effect transistor(MOSFET) integrated circuits. Annealing behaviors of coevaporatd tungsten silicide on P‐doped poly‐Si are studied by x‐ray diffraction, He+‐backscattering, transmission electron microscopy (TEM), and secondary ion mass spectroscopy (SIMS). High‐temperature annealing of silicides results in crystallization and homogenization of tungsten silicide as well as phosphorus out‐diffusion from the poly‐Si. Their effect on device fabrication is also discussed.

A quasi-two-dimensional analytical model for the turn-on characteristics of polysilicon thin-film transistors

Abstract: A physical model considering the effects of grain boundaries on the turn-on behavior of polysilicon thin-film transistors (poly-Si TFTs) is presented. Along the channel, the formation of the potential barrier near the grain boundary is proposed to account for the low transconductance and high turn-on voltage of TFTs. The barrier height is expressed in terms of channel doping, gate oxide thickness, grain size, and external gate as well as drain biases. Drain bias results in an asymmetric potential barrier and introduces more carrier injection from the lowered barrier side. It is shown that this consideration is very important for characterizing the saturation region under large drain-bias conditions. On the basis of the developed potential barrier model, the I-V characteristics are described by the interfacial-layer thermionic-diffusion model. Thin-film transistors on polycrystalline silicon with a coplanar structure were fabricated for testing. Comparisons show excellent agreement between the developed model and the experimental data. >

Porous polycrystalline silicon: a new material for MEMS

Abstract: A new technique for the fabrication of thin patterned layers of porous polycrystalline silicon (polysilicon) and surface micromachined structures is presented. First, a multilayer structure of polysilicon between two layers of low-stress silicon nitride is prepared on a wafer of silicon. Electrochemical anodization with an external cathode takes place in an RF solution. A window in the outer nitride layer provides contact between the polysilicon and the HF solution; the polysilicon layer contacts the substrate through openings in the lower silicon nitride layer (remote from the upper windows). Porous polysilicon growth in the lateral direction is found at rates as high as 15 /spl mu/m min/sup -1/ in 12M (25%, wgt) HF to be controlled by surface-reaction kinetics. A change in morphology occurs when either the anodic potential is raised or the HF concentration is decreased, causing the polysilicon to be electropolished. The etch front advances proportionally to the square root of time as expected for a mass-transport-controlled process. Similar behavior is observed in HF anodic reactions of single-crystal silicon. Dissolution of the polysilicon layer is confirmed using profilometry and scanning electron microscopy. Enclosed cavities (chambers surrounded by porous plugs) are formed by alternating between pore formation and uniform dissolution. Porous polysilicon also forms over a broad-area layer of polycrystalline silicon that has been deposited without overcoating the silicon wafer with a thin film of silicon nitride. The resulting porous layer may be useful for gas-absorption purposes in ultrasonic sensors. >

Adhesion and Friction Issues Associated With Reliable Operation of MEMS

Abstract: A growing interest exists in developing technologies that use silicon and other electronic materials as mechanical materials. Using standard processes of the integrated-circuit industry, researchers have successfully fabricated miniature mechanical components (micromachines) such as membranes, gears, motors, pumps, and valves. The integration of miniaturized mechanical components with microelectronic components has spawned a new technology known as microelectromechanical systems (MEMS). It promises to extend the benefits of microelectronic fabrication to sensing and actuating functions. Early applications of this technology include the digital mirror display, which has of the order of 106 aluminum thin-film micromirrors fabricated on top of a complementary-metal-oxide-semiconductor static random-access-memory integrated circuit. Other applications include integrated accelerometers for tasks such as air-bag deployment.A number of fabrication techniques have been developed for this technology and have been reviewed elsewhere. In this review, I focus on surface-micromachining technology and adhesion and friction problems in surface-micromachined polycrystalline silicon (polysilicon) structures, though many of the principles discussed will also apply both to single-crystalline silicon and nonsilicon-based structures. Surface micromachining, defined as the fabrication of micromechanical structures from deposited thin films, is one of the core technological processes underlying MEMS. Surface microstructures have lateral dimensions of 50-500 μm with thicknesses of 0.1–2.5 μm and are offset 0.1–2 μm from the substrate. The basic steps in a surface-micromachining process appear in Figure 1. First the substrate is typically coated with an isolation layer (Figure la) that protects it during subsequent etching steps. A sacrificial layer is then deposited on the substrate and patterned. For simplicity, Figure 1b shows that the opening of the sacrificial layer is terminated on the isolation layer. The microstructural thin film is then deposited and etched (Figure 1c). Finally selective etching of the sacrificial layer creates the freestanding micromechanical structures such as the cantilever beam shown in cross section in Figure 1d. The technique can be extended to make multiple-layer microstructures.