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Polysilicon depletion effect

About: Polysilicon depletion effect is a(n) research topic. Over the lifetime, 3327 publication(s) have been published within this topic receiving 50599 citation(s).
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Patent
Jack H. Yuan1, Eliyahou Harari1
15 Mar 1989-
Abstract: An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.

455 citations


Journal ArticleDOI
Abstract: The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 A, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 A drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.

294 citations


Journal ArticleDOI
Abstract: The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.

273 citations


Patent
11 Aug 1999-
Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

228 citations


Patent
31 Mar 2008-
Abstract: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

228 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20181
201716
201623
201538
201436
201358

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Topic's top 5 most impactful authors

Horng-Huei Tseng

22 papers, 298 citations

Charalabos A. Dimitriadis

20 papers, 497 citations

Mark I. Gardner

14 papers, 328 citations

G. Kamarinos

13 papers, 220 citations

Hisashi Shichijo

10 papers, 460 citations