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Polysilicon depletion effect

About: Polysilicon depletion effect is a research topic. Over the lifetime, 3327 publications have been published within this topic receiving 50599 citations.


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Patent
Jack H. Yuan1, Eliyahou Harari1
15 Mar 1989
TL;DR: In this article, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed.
Abstract: An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.

455 citations

Journal ArticleDOI
TL;DR: In this article, the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally, and it is shown that an increase in grain size from 230 to 1220 A drastically reduces the sensitivity to doping levels by two orders of magnitude.
Abstract: The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 A, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 A drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.

298 citations

Journal ArticleDOI
TL;DR: The anomalous leakage current I L in LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed.
Abstract: The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.

275 citations

BookDOI
10 Oct 2012
TL;DR: Polycrystalline Silicon for Integrated Circuits and Displays, Second Edition as mentioned in this paper presents much of the available knowledge about polysilicon, and it represents an effort to interrelate the deposition, properties, and applications of poly-silicon.
Abstract: Polycrystalline Silicon for Integrated Circuits and Displays, Second Edition presents much of the available knowledge about polysilicon. It represents an effort to interrelate the deposition, properties, and applications of polysilicon. By properly understanding the properties of polycrystalline silicon and their relation to the deposition conditions, polysilicon can be designed to ensure optimum device and integrated-circuit performance. Polycrystalline silicon has played an important role in integrated-circuit technology for two decades. It was first used in self-aligned, silicon-gate, MOS ICs to reduce capacitance and improve circuit speed. In addition to this dominant use, polysilicon is now also included in virtually all modern bipolar ICs, where it improves the basic physics of device operation. The compatibility of polycrystalline silicon with subsequent high-temperature processing allows its efficient integration into advanced IC processes. This compatibility also permits polysilicon to be used early in the fabrication process for trench isolation and dynamic random-access-memory (DRAM) storage capacitors. In addition to its integrated-circuit applications, polysilicon is becoming vital as the active layer in the channel of thin-film transistors in place of amorphous silicon. When polysilicon thin-film transistors are used in advanced active-matrix displays, the peripheral circuitry can be integrated into the same substrate as the pixel transistors. Recently, polysilicon has been used in the emerging field of microelectromechanical systems (MEMS), especially for microsensors and microactuators. In these devices, the mechanical properties, especially the stress in the polysilicon film, are critical to successful device fabrication. Polycrystalline Silicon for Integrated Circuits and Displays, Second Edition is an invaluable reference for professionals and technicians working with polycrystalline silicon in the integrated circuit and display industries.

231 citations

Patent
11 Aug 1999
TL;DR: In this article, a diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit, and the container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the material.
Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

228 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20237
20229
20181
201716
201623
201538