Polysilicon depletion effect

About: Polysilicon depletion effect is a research topic. Over the lifetime, 3327 publications have been published within this topic receiving 50599 citations.

Improved reliability for gate dielectric of low-temperature polysilicon thin-film transistors by NO-plasma nitridation

Abstract: Low-temperature polysilicon thin-film transistors (poly-Si TFTs) fabricated under 600 °C are treated with nitridation using NO plasma. Samples with nitrided gate oxide, nitrided active polysilicon, or both layers nitrided are produced respectively to compare their reliability. It is found that all the nitrided devices demonstrate improved reliability over the control one under both high-field and hot-carrier stresses. Moreover, nitridation on the oxide produces better results under high-field stress while nitridation on the polysilicon is better under hot-carrier stress. The effectiveness of this low-temperature plasma nitridation on TFTs makes the process potentially applicable to the production of high-quality flat-panel displays on glass substrate.

P-type control gate in non-volatile storage

Abstract: Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

Cryogenic behaviors of polysilicon emitter bipolar transistors and ECL circuits

Abstract: Some important parameters of polysilicon emitter bipolar transistors and the main characteristics of an ECL gate are studied experimentally and theoretically at low temperature. Based on them, optimization of a low temperature ECL circuit can be realized.

Analysis of Thermal Effect on the Interfacial Oxide between Polysilicon and Silicon for Polysilicon Bipolar Transistors by Capacitance and Contact Resistance Measurements

Abstract: Thermal effect on the interfacial oxide between polysilicon and silicon doped with arsenic was analyzed by capacitance and contact resistance measurements. The annealing temperature was varied from 850° C to 1000° C and, with the increase of annealing temperature, the oxide breakup was enhanced and the contact resistance decreased. It is shown for the first time that the capacitance also decreased with the increase of annealing temperature. This suggests that the interfacial area of the oxide layer decreases and the oxide layer thickness increases due to the oxide breakup. Capacitance characteristics are also compared with bipolar transistor characteristics.