Power-flow study

About: Power-flow study is a research topic. Over the lifetime, 8091 publications have been published within this topic receiving 155053 citations. The topic is also known as: load-flow study.

Emerging on-board power architectures

Abstract: In recent years, the feature size of silicon devices has decreased at a steady rate. Each step in feature size has required a reduction in operating voltage. As today's system designers seek to maximize performance, they use a wide variety of integrated circuits. The result is a system that requires many different supply voltages for various devices in the system. It is not unusual for a system today to require seven or eight different voltages and systems with twelve or more voltages are not uncommon. To meet this challenge, the traditional distributed power architecture has been extended to create the intermediate bus architecture. This paper explores the Intermediate Bus Architecture and highlights areas of special concern to system and power system developers.

Electrothermal coordination part II: case studies

Abstract: The concept of electrothermal coordination (ETC) in power system operation introduced in Part I proposes to exploit thermal inertia to coordinate line temperature dynamics with existing power system controls, thus increasing power transfer capability and enhancing system security and economic performance. In this Part II, the characteristics of ETC and its benefits in operational functions such as augmenting power transfer capability, emergency control, congestion management, and system loadability are numerically analyzed through a number of case studies. This paper also examines some practical issues concerning the deployment of ETC.

Power emulation: a new paradigm for power estimation

Abstract: In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it "power estimation hardware", and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

Impact assessment of LV distributed generation on MV distribution network

Abstract: Utility power systems are faced to an increasing number of small size producers requiring interconnection particularly to the low voltage (LV) network. Since most distribution systems are not designed to "receive" large scale power injections, these small generation units may impact these networks specifically in terms of quality of the energy delivered, reliability and safety of the whole distribution system from LV to medium voltage (MV) levels. In this paper, a methodology, based on a parametric study, is proposed to investigate distributed generation (DG) impacts when interconnected to distribution networks. The proposed methodology has been validated for a particular case of voltage profile (LV/MV). The test system used for this study is a real urban network containing 11 feeders with 2 transformers of 36 MVA.

Solution of Large Networks by Matrix Methods

Abstract: General Background Matrix Algebra Extensions of the Z-Matrix Short-Circuit Program to Include Very Large Systems Single-Phase Short Circuits State-Estimation Load Flow Solutions The Economics of Operating a Power System Optimum Load Flow Transient Stability High-Speed Reduced-Accuracy Power Flow Calculations for Contingency Evaluation and Maximum Interchange Capability Determinations Appendixes Index.