Showing papers on "Power integrity published in 2001"

Graphical user interface to integrate third party tools in power integrity analysis

Abstract: A power integrity analysis integration tool for analyzing the power integrity of a semiconductor layout previously designed using a separate design tool. The power integrity analysis integration tool includes a graphic user interface that is configured to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout. A method of designing a semiconductor layout and performing a transistor-level analysis of the power integrity of the semiconductor layout includes, first, using a design tool to design the semiconductor layout, and then using the power integrity analysis integration tool to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout.

High bandwidth low latency chip to chip interconnects using high performance MLC glass ceramic POWER4/sup R/ MCM

Abstract: This paper describes a high performance multi-layer ceramic (MLC) four chip glass-ceramic multi-chip module (MCM) that achieves very high bandwidth and low latency performance by incorporating unique design approaches and features. These include leveraging an I/O ring pattern arrangement using the fine line capability of IBM's High Performance Glass Ceramic (HPGC) and the capability to use 30+ wiring layers with isolating reference planes. The attendant signal integrity is assured by providing a tailored reference structure to control impedance and cross-talk coupling while maintaining the chip C4 I/O area density without requiring thin-films or degrading the power integrity.