Showing papers on "Power integrity published in 2004"

Electromagnetic interference (EMI) of system-on-package (SOP)

Abstract: Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits. Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims). This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement. First, LSI designs are discussed with regard to radiated emission. The signal-return path loop and switching current in the power/ground line are inherent sources of EMI. The EMI of substrate, which work as coupling paths or unwanted antennas, is described. Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI). In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI). Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems. Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems. This paper is expected to be useful in the design and development of SOPs that take EMI into consideration.

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

Abstract: From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

High-speed circuit board signal integrity

Abstract: As circuit boards are increasingly required to transmit signals at higher and higher speeds, signal and power integrity become increasingly crucial. Rules of thumb that you have used over and over again to prevent signal loss no longer apply to these new, high-speed, high-density circuit designs. This leading-edge circuit design resource offers you the knowledge needed to quickly pinpoint transmission problems that can compromise your entire circuit design. Discussing both design and debug issues at gigabit per second data rates, the book serves as a practical reference for your projects involving high-speed serial signaling on printed wiring boards. Step-by-step, this book goes from reviewing the essentials of linear circuit theory, to examining practical issues of pulse propagation along lossless and lossy transmission lines. It provides detailed guidelines for crosstalk, attenuation, power supply decoupling, and layer stackup tradeoffs (including pad/antipad tradeoffs). Other key topics include the construction of etched conductors, analysis of return paths and split planes, microstrip and stripline characteristics, and SMT capacitors. Filled with on-the-job-proven examples, this hands-on reference is the book that you can turn to time and again to design out and troubleshoot circuit signal loss and impedance problems.

Thermal and power integrity based power/ground networks optimization

Abstract: With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects on transistor and interconnect performance are well-studied, the interactions between power-delivery and thermal effects are not clear. As a result, power-delivery design without thermal consideration may cause soft-error, reliability degradation, and even premature chip failures. In this paper, we propose a thermal-aware power-delivery optimization algorithm. By simultaneously considering thermal and power integrity, we are able to achieve high power supply quality and thermal reliability. For a 58/spl times/72 mesh as shown in the experimental results, our algorithm shows that the lifetime of the optimized ground network is 9.5 years. Whereas the lifetime of the ground network generated by a traditional method is only 2 years without thermal concern.

Efficient power/ground network analysis for power integrity-driven design methodology

Abstract: As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear scaling of the threshold voltage that makes the ratio of the threshold voltage to the supply voltage rise, the voltage (IR) drop become a serious problem in modern VLSI design. Traditional power/ground (P/G) network analysis methods are typically very computationally expensive and thus not feasible to be integrated into floorplanning. To make the integration of the P/G analysis with floorplanning feasible, we need a very efficient, yet sufficiently accurate analysis method. In this paper, we present the methods for the fast analysis of the P/G networks at the floorplanning stage and integrate our analyzer into a commercial tool to develop a power integrity (IR drop) driven design methodology. Experimental results based on three real-world circuit designs show that our P/G network analyzer is accurate enough and very efficient.

First- and second-level packaging of the z990 processor cage

Abstract: In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

Evolution of organic chip packaging technology for high speed applications

Abstract: The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

Static and quasi-dynamic load balancing in parallel FDTD codes for signal integrity, power integrity, and packaging applications

Abstract: The finite-difference time-domain (FDTD) method is a robust technique for calculating electromagnetic fields, but practical problems, involving complex or large geometries, can require a long time to calculate on any one single-processor computer. One computer with many processors or many single-processor computers can reduce the computation time. However, some FDTD cell types, e.g., PML cells, require more computation time than others. Thus, the size and shape of the individual process allocations can significantly influence the computation time. This paper addresses these load balancing issues with static and quasi-dynamic approaches. The message-passing interface (MPI) library is applied to a three-dimensional (3D) FDTD code. Timing results including speedup and efficiency, are presented for trials run on a cluster of sixteen processing nodes and one server node. Two examples are shown in this paper, a power bus with 16 decoupling capacitors and a five layer power distribution network. In such models, the problem size and complexity make modeling with a serial code impractical and time consuming for engineering. Models with several million cells take days to run, but proper implementation, including load balancing, can reduce this execution time to hours on a sufficiently powerful cluster.

Simulation study of power delivery performance on flip-chip substrate technologies

Abstract: The input impedance of finite utility plane structures is calculated accurately from the simulated package resonance data using a commercial signal integrity tool. The effect of the equivalent circuit parasitics of the utility planes and their contributions to power integrity are simulated on both digital and high-speed sections for the same die and package footprint on three different package substrate technologies. In addition, the effective loop inductance and package substrate DC resistance is also calculated from the package input impedance at low frequency range. These results are used to discuss the intrinsic relationships between the physical package structure such as stackup, utility plane shapes and via types to identify and minimize the potential sources of package utility plane noise for critical applications.

Modelling the dynamic response of on-chip decoupling capacitors

Abstract: High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.

Power delivery modeling and design methodology for a programmable logic device package

Abstract: A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.

Sensitivity analysis of generic on-chip /spl Delta/I-noise simulation methodology

Abstract: Power integrity, i.e. providing a stable voltage supply under the condition of rapidly changing current transients, gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip /spl Delta/I-noise. Various simulation methodologies, e.g. RAPiD, are known for simulation. Characteristic for these simulations is the very time consuming task of collecting and processing the complex input data, in order to optimise the required effort a sensitivity analysis for high-frequency on-chip /spl Delta/I-noise simulation has been carried out. This paper describes the results of this sensitivity analysis. A generic description of the on-chip /spl Delta/I-noise simulation methodology is shown. In particular the required input data is described. The sensitivity analysis quantifies the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5x to 2.0x compared to a nominal case. The maximum HF /spl Delta/I-noise is measured and plotted versus the respective input parameter deviation. The input parameters are categorized in high, medium and low impact parameters. This analysis results in guidelines which design parameters most efficiently reduce HF-noise and/or which input parameter need to be accurate in order to obtain accurate simulation results.

A novel decoupling capacitance platform for substrates, sockets, and interposers

Abstract: Due to increasing demands on the power delivery networks within current and next-generation computer systems, power integrity has become a leading focus, in addition to signal integrity, in system design. We will present a technology deployed within substrates, interposers, or sockets to enhance core power delivery. Our technology is comprised of a novel integration of decoupling capacitance between the core power nets and ground. This decoupling replaces the numerous decoupling capacitors suboptimally placed on traditional printed circuit boards (PCBs). The net result it lowered power supply noise and increased core power stability, permitting greater semiconductor switching frequency while reducing overall system cost. Studying actual system applications, we compare this technology to a wide range of expensive and largely ineffective decoupling strategies that have been proposed and even deployed, and demonstrate its superiority in both cost and performance.

Simultaneous switching noise analysis for full-chip power integrity sign-off

Abstract: This work describes an efficient methodology for the analysis of simultaneous switching noise in an integrated system of a microchip in its package and board environment. This methodology has been used to analyze and identify the noise from I/O cell simultaneous switching output (I/O SSO) on a large network processor design in 130 nm technology. This methodology provides a fast and accurate global I/O SSO analysis that can be applied during the design phase to identify I/O SSO effects and their impact on the core. The supply noise predicted by the I/O SSO analysis was correlated with full-chip results of a true dynamic AC noise analysis flow and verified with measurements on silicon.

Electromagnetic interference of system on package

Abstract: Electromagnetic interference (EMI) issues are expected to be crucial for next-generation system-on-package (SOP) integrated high-performance digital LSIs and for radio frequency (RF) and analog circuits Ordinarily in SOPs, high-performance digital LSIs are sources of EMI, while RF and analog circuits are affected by EMI (victims) This paper describes the following aspects of EMI in SOPs: 1) die/package-level EMI; 2) substrate-level EMI; 3) electromagnetic modeling and simulation; and 4) near electromagnetic field measurement First, LSI designs are discussed with regard to radiated emission The signal-return path loop and switching current in the power/ground line are inherent sources of EMI The EMI of substrate, which work as coupling paths or unwanted antennas, is described Maintaining the return current path is an important aspect of substrate design for suppressing EMI and for maintaining signal integrity (SI) In addition, isolating and suppressing the resonance of the DC power bus in a substrate is another important design aspect for EMI and for power integrity (PI) Various electromagnetic simulation methodologies are introduced as indispensable design tools for achieving high-performance SOPs without EMI problems Measurement techniques for near electric and magnetic fields are explained, as they are necessary to confirm the appropriateness of designs and to investigate the causes of EMI problems This paper is expected to be useful in the design and development of SOPs that take EMI into consideration

Full-chip multilevel routing for power and signal integrity

Abstract: Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-micron designs. We present a novel design methodology that simultaneously considers global signal routing and power network design under integrity constraints. The key part to this approach is a simple yet accurate power net estimation formula that decides the minimum number of power nets needed to satisfy both power and signal integrity constraints prior to detailed layout. The proposed design methodology is a one-pass solution to the co-design of power and signal networks in the sense that no iteration between them is required in order to meet design closure. Experiment results using large industrial benchmarks show that compared to the state-of-the-art alternative design approach, the proposed method can reduce the power network area by 19.4% on average under the same signal and power integrity constraints with better routing quality, but use less runtime.

Congestion and Power Integrity Aware Placement and Routing for 3D Packaging

Abstract: One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion tradeoff. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.

Full Chip Signal and Power Integrity with Silicon Substrate Effect

Abstract: This paper proposes a new method for analyzing signal and power integrity issues on LSI chips. This method can model a full chip power and ground grids considering the effects of transmission line and silicon substrate. A full chip layout data is divided into sections, then each section is modeled as SPICE transmission lines. N-port parameters of the each section are extracted by newly developed super linear solver. The extracted parameters are converted into compact SPICE frequency table. Using this method, the impedance of power/ground grids and dynamic IR drop for signal traces considering full power/ground grids are analyzed. Authors’ Biography Norio Matsui Norio Matsui holds a Ph. D. from Waseda University, Tokyo and was a researcher in NTT Labs for over 16 years. During this period he developed noise simulators integrated with PCB-CAD for Signal and Power Integrity as well as physical designs for high speed tele-switching systems. Apart from authoring numerous papers, he also lectured at Chiba University. He is currently President of Applied Simulation Technology and is actively involved in Power Integrity, Signal Integrity, and EMI/EMC solutions. Dileep Divekar Dileep Divekar obtained a B.S. in Electrical Engineering from Pune University, Pune, India and M.S. and Ph.D. in Electrical Engineering from Stanford University, Stanford, CA. He has worked in the areas of circuit simulation, semiconductor device modeling, static timing analysis and signal integrity. He is currently Vice President of Applied Simulation Technology. Neven Orhanovic Neven Orhanovic received his B.S. degree in Electrical Engineering from the University of Zagreb, Croatia and his M.S. and Ph. D. degrees in Electrical and Computer Engineering from Oregon State University, Corvallis. From 1992 until 1999, he was with Interconnectix and Mentor Graphics Corp. developing numerical methods and simulation software in the area of interconnect analysis and interconnect synthesis. He is currently with Applied Simulation Technology working mainly on fullwave analysis methods Hiroshi Wabuka Hiroshi Wabuka received the M.S. degree in electrical engineering from Himeji Institute of Technology in 1982. He joined the semiconductor group, NEC in 1982 and was responsible for CMOS VLSI circuit design. He is a principal researcher in Jisso research laboratory, NEC and his responsibility is LSI modeling for packaging design and EMC analysis.

Sensitivity Analysis for On-Chip AI-Noise Simulation

Abstract: Power integrity gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip AInoise. Some simulation methodologies, e.g. RAPiD, are known for simulation. Collecting and processing the required input for these simulations is very time consuming. This paper presents a sensitivity analysis for high-frequency on-chip power noise distribution, The results help to optimize the effort required to achieve the needed accuracy of simulation. A generic description of the on-chip AI-noise simulation methodology is shown. In particular the required input data is described. A sensitivity analysis has been performed to quantify the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5~ to 2.0~ compared to a nominal case. The maximum AI-noise is plotted depending on the input parameter. The comparison to the nominal case shows which of the parameters have a high, medium or low impact on the simulated AI-noise. This paper shows which input parameter need to he accurate in order to obtain accurate simulation results.