Showing papers on "Power integrity published in 2007"

Power Integrity Modeling and Design for Semiconductors and Systems

Abstract: The First Comprehensive, Example-Rich Guide to Power Integrity ModelingProfessionals such as signal integrity engineers, package designers, and system architects need to thoroughly understand signal and power integrity issues in order to successfully design packages and boards for high speed systems Now, for the first time, there's a complete guide to power integrity modeling: everything you need to know, from the basics through the state of the artUsing realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noiseThe authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applicationsThe authors Introduce power delivery network components, analysis, high-frequency measurement, and modeling requirements Thoroughly explain modeling of power/ground planes, including plane behavior, lumped modeling, distributed circuit-based approaches, and much more Offer in-depth coverage of simultaneous switching noise, including modeling for return currents using time- and frequency-domain analysis Introduce several leading time-domain simulation methods, such as macromodeling, and discuss their advantages and disadvantages Present the application of the modeling methods on several advanced case studies that include high-speed servers, high-speed differential signaling, chip package analysis, materials characterization, embedded decoupling capacitors, and electromagnetic bandgap structures This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists It will also be valuable to developers building software that helps to analyze high-speed systems

Structured and parameterized model order reduction

Abstract: Model-order reduction techniques are described for RLC circuits modeling the VLSI layouts. A structured model order reduction is developed to preserve the block-level sparsity, hierarchy and latency. In addition, a structured and parameterized model order reduction is developed to generate macromodels for design optimizations of VLSI layouts. The applications are thermal via allocation under the dynamic thermal integrity and via stapling to simultaneously optimize thermal and power integrity.

Power Supply Noise in SoCs: Metrics, Management, and Measurement

Abstract: Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of predictability is complicating timing closure, physical design, production test, and speed grading of SoCs. This article describes and validates two metrics that quantify the impact of power supply noise. The IC industry is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. These advanced technologies pose unexpected challenges to the semiconductor industry. The DSM problems have led the development of SOC design methodologies to deal with the problem of complexity and productivity. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations. Dynamic voltage drop (DVD) analysis is emerging as a replacement of SVD analysis for capturing the impact of power supply noise on the timing behavior of logic and memory cells.

Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity

Abstract: With high integration density of today's electronic system and reduced noise margins, maintaining high power integrity becomes more challenging for high performance design. Inserting decoupling capacitors is one important and effective solution to improve the power integrity. The existing decoupling capacitor optimization approaches meet constraints on input impedance. In this paper, we show that impedance metric leads to large overdesign and then develop a noise-driven optimization algorithm for decoupling capacitors in packages for power integrity. We use the simulated annealing algorithm to minimize the total cost of decoupling capacitors under the constraints of a worst case noise bound. The key enabler for efficient optimization is an incremental worst case noise computation based on fast Fourier transform over incremental impedance matrix evaluation. Compared to the existing impedance-based approaches, our algorithm reduces the decoupling capacitor cost by 3times and is also more than 10times faster even with explicit noise computation

Chip Power Model - A New Methodology for System Power Integrity Analysis and Design

Abstract: A compact SPICE equivalent circuit model of full-chip power network is proposed in this paper to address the system power integrity co-design and optimization. The theory and procedures for the generation of the compact chip power model is described. The accuracy validation of the chip power model is also presented.

Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement

Abstract: Power integrity is a crucial design issue for nano-meter technologies because of decreased supply voltage and increased current. We focused on gate delay variation caused by power/ground noise, and developed a full-chip simulation current model with capacitance and a variable resistor to accurately model current dependency on voltage drop. Measurement results for 90-nm technology are well reproduced in simulation. The error of average supply voltage is 0.9% in average. Measurement results also demonstrate that gate delay depends on average voltage drop.

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Abstract: Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

Abstract: This paper proposes noise-direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constraints have led microprocessor designers to incorporate aggressive power saving techniques such as clock-gating, that place a significant burden on the power delivery network. While the application of extensive clock-gating can effectively reduce power consumption, unfortunately, it can also induce large inductive noise (di/dt), resulting in signal integrity and reliability issues. To combat these problems, processors are usually designed for the worst-case current consumption scenario using adequate supply voltage and decoupling capacitances. To tackle high-frequency inductive noise and potential IR drops, we propose a novel design methodology that integrates microarchitectural profiling feedback into the floorplanning process. We present two microarchitectural metrics to quantify the noise susceptibility of a module:self weighting and correlation weighting. By using these metrics in a force-directed floorplanning algorithm to assign power pin affinity to modules, we can quickly converge to a design for average-case current consumption. By designing for the average-case and employing dynamic di/dt control for the worst-case, we can ensure that a chip is noise-tolerant without exceeding decap budget constraints. Our observations showed that certain functional modules in a processor exhibit consistent and highly correlated switching activity, that can be used to guide module placement distance from power pins. The experimental results demonstrate that the force-directed floorplanning technique can effectively suppress supply noise experienced by modules, reduce the total number of supply-noise margin violations, and achieve a floor-plan with considerably lower IR drop, as compared to a wire-length driven floorplan.

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and

Abstract: This paper presents a numerical approach that com- bines the finite-element time-domain (FETD) method and the fi- nite-difference time-domain (FDTD) method to model and ana- lyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise (SSN) induced by adjacent signal traces through the coupled-via parallel-plate structures. Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD flexibility and FDTD efficiency. By further including the transmis- sion-line simulation, the signal integrity and power integrity is- sues can be resolved at the same time. Furthermore, the numer- ical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation. Finally, a com- parison with the measurement data validates the proposed hybrid techniques. Index Terms—Differential signaling, finite-element and finite- difference time-domain (FETD/FDTD) methods, power integrity (PI), signal integrity (SI), simultaneous switching noise (SSN), transient analysis.

Comparative Analysis of Electrical Performance on Coreless and Standard Flip-Chip Substrate

Abstract: In recent years, more and more devices are designed by high-performance flip-chip ball grid array (FCBGA) packages due to the requirement on large number of I/O pads, small pitch, and high operation frequency of ASIC. Many studies were done on FCBGA packages. Some of these works were focused on thinner structures. In the study of this paper, our targets will be focused on the coreless and standard FCBGA cases. By directly replacing the BT-core of the standard substrate with a thinner build-up dielectric layer, the coreless design is a good choice to decrease the cost. This replacement makes some differences between the standard thick BT-core and the new thinner build-up substrates. Our study analyzes the electrical performance caused by these differences. With the simulation approach, the analyses include the power integrity (PI) and signal integrity (SI) issues in frequency and time domains on both coreless and standard substrates. In the final results, we found that the coreless substrates could get a better electrical performance, for examples, the smaller coupling between the signal nets, the lower impedance of the power delivery system. The results from these analyses could give a useful reference for chip designers while they make a decision on package.

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and Finite-Difference Time-Domain Techniques

Abstract: This paper presents a numerical approach that combines the finite-element time-domain (FETD) method and the finite-difference time-domain (FDTD) method to model and analyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise (SSN) induced by adjacent signal traces through the coupled-via parallel-plate structures. Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD flexibility and FDTD efficiency. By further including the transmission-line simulation, the signal integrity and power integrity issues can be resolved at the same time. Furthermore, the numerical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation. Finally, a comparison with the measurement data validates the proposed hybrid techniques.

Progress in representation and validation of physics-based via models

Abstract: Vias in printed circuit boards and chip packages are known to have significant detrimental impact on signal and power integrity in high-speed communication systems. Recently, concise equivalent circuit models for vias in multilayer configurations have been explored by the authors. The models accurately reflect the important physical properties of vias, since the topology utilized has a one-to-one correlation to the geometrical structure and the dimensions of the via. In this paper, the proposed physics-based via models are extended to include the interaction between two signal vias and a signal via plus a reference (ground) via. The models were then compared to experimental data obtained from several structures laid out on a 16-layer printed circuit board. The measurements performed using a 4-port vector network analyzer and the high performance recessed probe launching technique evidenced good correlation to 20 GHz and beyond.

Modeling of Advanced Multilayered Packages with Multiple Vias and Finite Ground Planes

Abstract: A system-level modeling approach, which combines the MoM (method of moments) and the SMM (scattering matrix method) has been presented for the modeling of advanced electronic packages (Oo et al., 2007). The focus of this paper is on addressing the problems of multilayered multiple via coupling and finite ground effects by the SMM method. Significant extensions of the SMM method facilitate the modeling of coupling among densely populated vias in multilayered packages with finite power/ground planes. The proposed approach is suitable for the signal and power integrity, and even EMI analysis of packages at system level.

Computationally efficient power integrity simulation for system-on-package applications

Abstract: Power integrity simulation for system-on-package (SoP) based modules is a crucial bottleneck in the SoP design flow. In this paper, the multi-layer finite difference method (M-FDM) augmented with models for split planes has been proposed as a fast and accurate frequency domain engine. Results demonstrating the accuracy and scalability of the method have been presented. In particular, the algorithm was employed to the analysis of a realistic 6 layer package with ~ 200k nodes.

Coupled Analysis of Quasi-static and Full-Wave Solution towards IC, Package and Board Co-design

Abstract: In this paper, cascade-related approach and global one-single model methodology are investigated and compared in reference to real-world System-in-Package (SiP) product, which is designed using Cadence-SiP, and analyzed using Optimal SiP-enabled tool suite. A complete multi-level path, which consists of three portions-integrated circuit (IC), package and printed-circuit-board (PCB) -is selected as a test vehicle to investigate the limit of cascade-based approach. The results from quasi-static and full-wave simulation are compared, and the advantage of full-wave as well as limitation of quasi-static model are discussed. An innovative concept, referenced as "residual S-parameter", is proposed to characterize the coupling at the interface of IC, package and PCB, which plays an important role in the cascading of individual modules. Impact of the proposed concept on power integrity (PI) and signal integrity (SI) analysis is emphasized. Comparisons between full-wave, quasi-static and measurement results for representative component elements (interconnect, coupled bond wires) are discussed.

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm

Abstract: This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20--100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.

Signal and Power Integrity Co-Simulation for Multi-layered System on Package Modules

Abstract: The coupling of simultaneous switching noise (SSN) in mixed signal system on package modules is a critical signal and power integrity (SI/PI) problem. In the presence of split planes and apertures, SSN coupling occurs both horizontally as well as vertically across layers. Thus, to catch SI and PI problems at an early stage of design requires fast signal and power co-simulation methodologies. In this paper, we outline the multi-layer finite difference method and how the accuracy of the technique can be enhanced with models for fringe and gap effects. We then briefly describe a method for integrating the signal distribution network with the power distribution network to enable co-simulation. The method is then applied to a mixed signal board containing split planes, and numerical results are compared to full-wave simulations.

Power and Signal Integrity and Electromagnetic Emission; the Balancing Act of Decoupling, Planes and Tracks

Abstract: The noise voltage in the reference or ground of a printed circuit board is often the cause of unwanted radiated emission. Power supply planes attribute to the noise voltage. By replacing the power supply planes by tracks, the noise voltage in the reference or ground can be considerably reduced, which leads to a dramatic reduction of the radiated electromagnetic fields. This has been shown using transmission line equations for a general two-conductor line. Simulation and measurements results confirm the beneficial effect of removing power planes. A reduction of 50 dB in radiated electromagnetic field strength was obtained. The question was raised whether (or not) the signal integrity is negatively influenced by using power tracks instead of planes. Several printed circuit boards have been built and measured, showing that signal integrity remains while reduction of radiated emission is achieved.

Modeling of Signal and Power Integrity in System on Package Applications

Abstract: We present a method for fast analysis of signal and power integrity in system-on-package applications based on a recently developed multilayered finite difference method (M- FDM). First we present a rapid solver that can be used to extract materials properties of dielectrics. The extracted frequency- dependent dielectric constant and loss tangent can then be used in any field simulator for improved accuracy. Then we present M- FDM for simulation of system-on-package applications. In order to accurately model multilayered planar structures, which are three dimensional, M-FDM combines two-dimensional models for power/ground planes using a multilayered unit cell approach. In this way, noise coupling can be considered not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. For a co-simulation of signal and power integrity, transmission line models also need to be included. The interaction between the signal transmission and power distribution modes is taken into account using a modal decomposition technique. An equivalent circuit model becomes available based on this finite difference approximation as well. Based on this network representation, second order effects such as fringe and gap fields can be included in M-FDM using equivalent circuit models for these fields. This results in a very accurate method that can be used for fast analysis of signal and power integrity in arbitrary package and board designs having any stack-up configuration and number of layers.

FPGA Design for Signal and Power Integrity

Abstract: FPGAs have traditionally been optimized for low-cost environments where signal and power integrity are minor considerations. With today’s requirements for high-speed memory and serial interfaces, FPGA silicon and packages must be designed to provide good signal and power integrity while still maintaining cost objectives. Performance goals for nearand far-end simultaneous switch noise (SSN) noise as well as power supply quality are the primary metrics. Both nearand far-end noise is generated when all drivers switch concurrently creating SSN. Mutual coupling from aggressor signals to victims and delta-I noise associated with the inductance of power and ground paths are the primary mechanisms that cause noise during the rise time of the aggressors. The di/dt of the aggressors is responsible for this noise. Both horizontal structures (transmission lines and planes) and vertical structures (bumps, balls, and vias) contribute to SSN crosstalk. The vertical structures are responsible for most of the noise. Neither nearnor far-end noise should exceed 50 percent of the signal noise margin. This goal is achieved by controlling the signal I/O to power and ground ratios. The quality of the power supply, seen by the circuits on the die, is important for proper circuit performance and the ability to meet timing and jitter specifications. The power distribution network (PDN) for the package die combination is an important consideration in determining power supply quality. Through the use of on-package decoupling (OPD) capacitance and on-die capacitance (ODC), the power supply voltage tolerance is held to +/-10 percent of nominal throughout the difficult die/package resonance frequency band. This paper describes the design trade-offs made for the Altera Stratix III family of FPGAs to achieve performance while maintaining costs. Measured data on design prototypes as well as simulation predictions are presented.

Efficient decoupling capacitance budgeting considering operation and process variations

Abstract: This paper solves the variation-aware on-chip decoupling capacitance (decap) budgeting problem. Unlike previous work assuming the worst-case current load, we develop a novel stochastic current model, which efficiently and accurately captures operation variation such as temporal correlation between clock cycles and logic-induced correlation between ports. The models also considers current variation due to process variation with spatial correlation. We then propose an iterative alternative programming algorithm to solve the decap budgeting problem under the stochastic current model. Experiments using industrial examples show that compared with the baseline model which assumes maximum currents at all ports and under the same decap area constraint, the model considering temporal correlation reduces the noise by up to 5times, and the model considering both temporal and logic-induced correlations reduces the noise by up to 17times. Compared with the model using deterministic process parameters, considering process variation tLej f variation in this paper reduces the mean noise by up to 4times and the 3 sigma noise by up to 13times. While the existing stochastic optimization has been used mainly for process variation purpose, this paper to the best of our knowledge is the first in-depth study on stochastic optimization taking into account both operation and process variations for power network design. We convincingly show that considering operation variation is highly beneficial for power integrity optimization and this should be researched for optimizing signal and thermal integrity as well.

Mitigation of simultaneous switching noise in high speed circuit using electromagnetic bandgap structures with interdigial meander bridge

Abstract: An interdigital meander-bridge electromagnetic bandgap power/ground planes for suppressing simultaneous switching noise is presented The effective suppressing bandwidth of interdigital meander-bridge structure is from 880 MHz to 491 GHz Although it improves good power integrity, the pads between integrated squares and meander-bridge will destroy signal integrity problem The performance is determined by maximum eye open and maximum eye width The results show the present structure is superior to other structure for suppressing simultaneous switching noise and provide a better signal integrity

Analysis for Signal and Power Integrity Using the Multilayered Finite Difference Method

Abstract: We present a method for fast analysis of signal and power integrity based on a recently developed multilayered finite difference method (M-FDM). In order to accurately model multilayered planar structures, which are three dimensional, M-FDM combines two-dimensional models for power/ground planes using a multilayered unit cell approach. In this way, noise coupling can be considered not only in the transversal direction between two planes, but also vertically from one plane pair to another through the apertures and via holes. For a cosimulation of signal and power integrity, transmission line models also need to be included. The interaction between the signal transmission and power distribution modes is taken into account using a modal decomposition technique. An equivalent circuit model becomes available based on this finite difference approximation as well. Based on this network representation, second order effects such as fringe and gap fields can be included in M-FDM using equivalent circuit models for these fields. This results in a very accurate method that can be used for fast analysis of signal and power integrity in arbitrary package and board designs having any stack-up configuration and number of layers.

MPCG for Large-Current Using Ultra Low Loss Dust Material SENNTIX Formed by One-Piece Construction

Abstract: Recently, the performance of electronic equipment has been advancing rapidly and function availability has been increasing. This trend is of particular importance in the case of compact equipment such as notebook PCs, where a reduction in voltages in order to reduce the power consumption has resulted in an increase in the current flowing through the power lines. This has made it necessary for the inductors to be capable of dealing satisfactorily with the high-current supply and to improve the power loss characteristic. NEC TOKIN has started development of low-loss magnetic core materials that can improve power conversion efficiency and has produced an ultra low loss dust material for inductors, named "SENNTIX." "SENNTIX" is a metallic glass dust powder that features both a high saturated magnetic flux density that is proper to metallic materials and a stable amorphous structure proper to metal glass composite materials. There is no magnetic saturation under a high-current supply and it can therefore significantly reduce magnetic loss resulting from the effect of the core material. NEC TOKIN's low-loss choke coils of the MPCG Series use the low-loss metallic glass composite material "SENNTIX" as the core material and offer a high power conversion efficiency reflecting the low loss characteristic of the material. We are now advancing the application and deployment of "SENNTIX" in power components with the aim of providing solutions for power supply systems issues of electronic equipment that is subjected to increasing power loads. This policy will enable energy saving and control of heat generation as well as improvements in the power integrity.

A Novel Approach for System Level Package Modeling to Address Signal and Power Integrity Issues

Abstract: The electromagnetic compatibility simulation of the power delivery network inside the integrated circuit packaging becomes an important issue in the modern circuit design. In this paper, this complex power-ground plane is divided into the internal region and external region. These two regions are simulated by using the hybrid integral equations. The internal integral equation is described by using the rectangular cavity dyadic green functions, while the external integral equation is described by using the free-space green function. These two equations are coupled through the equivalent magnetic current placed on the periphery and gaps of the power-ground plane. This proposed method could accurately simulate both the coupling between vias inside the power-ground plane and the emission from the periphery and gaps of the power-ground plane. Through several examples, its accuracy and efficiency are validated.

Design of UWB Transceiver SiP for Short Range Communication

Abstract: Since UWB system uses a wide frequency range from 3.1 GHz to 5.1 GHz, package parasitic effects have been a hot issue which affects system malfunction. To prevent such malfunction, SiP technology is adjusted considering not only a circuit performance but various design issues in a package from viewpoints of signal integrity and power integrity. Furthermore, UWB band-pass filter is embedded into a package to reduce a complexity of transmitter circuit and the power consumption. Designed UWB SiP performance is verified by the measurement in time domain.

Application of Integral Analysis Technique to Determine Signal- and Power Integrity of Advanced Packages

Abstract: In this paper an application of an integral analysis technique is demonstrated for determining signal integrity (SI) and power integrity (PI) of complex and advanced package solutions. A representative system-in-package (SiP) product has been selected as a carrier for our study, which is focused on analysis methodology, tools and flow. In particular, possibility to easily support what-if simulations for SI and PI, including analysis with distributed on-chip decoupling capacitors is investigated and highlighted. Importance of balancing between accuracy, CPU time and ease-of-use is also underlined.

Study of High Speed Current Excitation Reverse Engineering Methodology Using Measured Voltage and PDN Impedance Profile from a Running Microprocessor

Abstract: Traditionally, power integrity engineer uses simulated transient current profile, icc(t) from the Circuit Designer as input to power delivery network, PDN to simulate worst case transient power noise. However, it is extremely difficult to simulate the maximum current profile from large circuit or logic block. It increases the difficulties when the circuit/ logic run at random application. The paper discusses the reverse engineering method to regenerate high speed stimulus current from the given PDN and measured voltage waveform. The paper firstly verified that the reverse engineering method proven to be accurate in HSPICE simulation. Then measurement technique is applied to an Intelreg Core 2 Duo Processor running stress test under various random applications. The paper also discusses the precision and reproducibility of high speed current profile, icc(t) by using this reverse engineering technique. The finding enables the transient power simulation of a PDN can be done without depending on the simulated CKT/ Logic block icc(t) data. The method also improves the correlation work to be done between the pre-silicon simulated icc(t) with the measurement data from the lab.

SI/PI/EMI Analysis of Through-Via Effects on Power/Ground Plane using High Dielectric Material

Abstract: In this paper, we simulated and analyzed about through-via's signal integrity, (SI)/power integrity, and (PI)/electromagnetic interference (EMI) that goes through the power/ground plane which was caused by the high dielectric material that supports the embedded high value capacitors. In order to evaluate through-via's effectiveness, the simulation condition was operated on the LTCC module for mixed signal system. For the circumstance SI, delay time of signal line and signal quality significantly decrease because of higher parasitic capacitance between through-via's and anti-pads. However, in a situation where the dielectric material is chosen, the EMI's characteristic power/ground plan with embedded high dielectric material shows a better characteristic than when the low dielectric material was chosen. As a result, if the high dielectric material is applied on LTCC module, the mixed module packaging that is made with the digital IC and RF component will be realized as the optimistic design. The simulation structure takes the LTCC process designer guidebook as a basic structure and uses the HFSS/designer tool. When the dielectric constant uses 7.8 and 500, the through-via's that pass through the LTCC module are delay time of 41.4 psec and 56, respectively. When the dielectric constant of 500 is compared with 7.8, the power/ground plane impedance shows a trait lower than several GHz range and effectiveness in the rejection of the resonance mode. When uses the dielectric constant is 500, the EMI level is 7.8 and it is prove that the EMI level improves at maximum 20 dB V/m.