Showing papers on "Power integrity published in 2009"

Signal and Power Integrity - Simplified

Abstract: The #1 Practical Guide to Signal Integrity DesignNow Updated with Extensive New Coverage!This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design. Drawing on his work teaching more than five thousand engineers, world-class signal and power integrity expert Eric Bogatin systematically reviews the root causes of all six families of signal integrity problems and shows how to design them out early in the design cycle. This editions extensive new content includes a brand-new chapter on S-parameters in signal integrity applications, and another on power integrity and power distribution network designtopics at the forefront of contemporary electronics design.Coverage includesA fully up-to-date introduction to signal integrity and physical designHow design and technology selection can make or break the performance of the power distribution networkExploration of key concepts, such as plane impedance, spreading inductance, decoupling capacitors, and capacitor loop inductancePractical techniques for analyzing resistance, capacitance, inductance, and impedanceSolving signal integrity problems via rules of thumb, analytic approximation, numerical simulation, and measurementUnderstanding how interconnect physical design impacts signal integrityManaging differential pairs and lossesHarnessing the full power of S-parameters in high-speed serial link applicationsEnsuring power integrity throughout the entire power distribution pathRealistic design guidelines for improving signal integrity, and much moreUnlike books that concentrate on theoretical derivation and mathematical rigor, this book emphasizes intuitive understanding, practical tools, and engineering discipline. Designed for electronics industry professionals from beginners to experts it will be an invaluable resource for getting signal integrity designs right the first time, every time.

Efficient 2-D Integral Equation Approach for the Analysis of Power Bus Structures With Arbitrary Shape

Abstract: A 2-D contour integral-equation method for the frequency-domain analysis of arbitrarily shaped power bus structures is presented. The numerically efficient approach allows the rapid and accurate computation of the frequency-dependent transfer parameters between an arbitrary number of ports, as required for embedding the power plane structure into network simulation. A formulation is developed for calculating the voltage distribution between the planes, as well as for determining the resulting radiated fields based on the field-equivalence principle. The method is applied for several test boards including a populated board with a surface-mount decoupling-capacitor network. The suggested approach is well confirmed by an analytical solution for the rectangular structure, by measurement and 3-D full-wave simulation results.

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Abstract: This paper proposes an all-digital measurement circuit called a ldquogated oscillatorrdquo to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a power-gating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3-5.9 Gsample/s with an area of 10.08 times 6.72 mum2, and the improved power gating structure achieved 6.6-8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity.

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

Abstract: This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.

Fundamental mechanisms of coupling between planar electromagnetic bandgap structures and interconnects in high-speed digital circuits. Part I - microstrip lines

Abstract: The paper studies the signal integrity performances of a microstripline routed over a planar EBG structure. The fundamental mechanisms of the coupling between the signal transmitted along the trace and the resonant properties of the same structure are investigated.

GPGPU-FDTD method for 2-dimensional electromagnetic field simulation and its estimation

Abstract: For signal/power integrity analysis of the high density packages and printed circuit boards, the FDTD (Finite-Difference Time-Domain) method has been widely used. In order to apply to large-scale problems, a variety of acceleration techniques are required. This paper describes a GPGPU-FDTD (General Purpose computing on GPU (Graphic Processing Unit)-Finite-Difference Time-Domain) method for massively parallel electromagnetic field simulation. Finally, it is confirmed that GPGPU-FDTD method shows the high-performance when the computational algorithm is programmed suitably for the architecture of GPU.

EMC-aware design on a microcontroller for automotive applications

Abstract: In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

Challenges and solutions for next generation main memory systems

Abstract: Today's high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view.

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Abstract: Integrated System Level Simulations of high speed serial links are necessary for the channel reliability and robustness. Increasing data rates and sharp transition time require high bandwidth systems. System level simulation are required to optimize channel design keeping cost of implementation at moderate or low level while meeting system level channel Bit Error Rate requirement for high bandwidth systems. The parameters which influence the channel and it's interconnect environment are primarily governed by signal integrity and power integrity requirements. In this paper, System Level Robustness Analysis of High Speed Serial Links is demonstrated with external environment considerations taken into account. A strong correlation between measured and simulated results is shown. A generic methodology for high speed serial links is presented with complete analysis of package, board, termination, Signal Quality inrush Droop/Drop (SQiDD), decoupling network etc. I. INTRODUCTION In Semiconductor industry due to tool limitations package analysis, board analysis, mixed signal simulations are performed separately. The complete channel performance is cumulative effect of whole interconnect environment consisting of transceiver, bond wire, package substrate, board, media/cable and termination environment. 'On-the- Board System' means die, package and board integrated together, to form a complete system. There is always a trade off between the various entities which form part of channel environment. In high speed transceivers, Signal Integrity (SI) and Power Integrity (PI) are the most important factors for the designers to keep in the mind while designing a system, as it affects the reliability of transmission at high data rates. This paper presents a Generic Flow for complete On-the- Board System Level Simulation to simulate and analyze the Reliability and Robustness of any PHY ( with example of USB 2.0 PHY), in context of high speed data transmission. Three advantages of SI and PI Analysis are: 1) This analysis is useful to perceive the behavior of whole system at simulation level accurately. 2) This can be used to ensure the Robustness and Reliability of a channel for the targeted bit error rate. 3) It will help the designers to modify the system before it is fabricated. Thus it will reduce product cost and minimize silicon iterations. II. SIGNAL AND POWER INTEGRITY AT SYSTEM LEVEL Signal Integrity means to preserve the signal as it propagates through the media between the transmitter and the receiver (i.e. without distortion in its amplitude shape and jitter performance). At higher speeds, board traces and package signal nets behave like transmission lines. In Serial Links (at system level), there are many types of losses/reflections that may cause distortion in signal quality e.g. reflection loss, insertion loss, coupling etc. Power Integrity (PI) deals with the power delivery network from a voltage source to active devices (ICs) through boards and packages. The noise in the power distribution network mainly affects the system jitter performance as jitter originates from the varying propagation delay caused by shifting bias levels in active circuits. This phenomenon is more prominent with shrinking technologies. Together this environment causes degradation in signal quality which can be primarily measured either by eye diagram or quantitatively by system Bit error rate.

Analysis of Complete Power-Distribution Network and Co-Design Optimization

Abstract: This paper describes the modelling analysis for a power-distribution network and demonstrates co-design and co-simulation in using the detailed prototype model, which includes a chip, package, and printed circuit board. A circuit simulator and a 2D solver using the finite element method are used to study the frequency and transient responses for the core switching noise. In the model, we assume a chip model (current profile and on-chip capacitance) and define the circuit parameters with an equivalent circuit to meet the target impedance. Then the physical design of the package and printed circuit board were done to check all of the required circuit parameters. According to the modelling and evaluation, the package design with a low equivalent series inductance capacitor in the bottom layer and a thin core structure is more advantageous than a capacitor in the top layer.

Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network

Abstract: In this paper, an efficient parallel flow for the design of the full power distribution network (PDN) is proposed. The analysis demonstrates the impact of the voltage regulator model in both frequency and time domain response. Based on the experimental results, it is observed that including the voltage regulator model in the PDN model increases the transient voltage drop and PDN response which need to be considered for nanoscale ICs. The flow is optimized using parallel processing to speedup slow response simulation time of the off chip voltage regulator. The study highlights the power integrity issues related to voltage regulator in broadband frequency ranges. The experimental results show speedup of up to 22 times with single processor and more than 430 times using up to 200 processors compared to HSPICE and other commercial simulators. The PDN simulation time is reduced from hours to less than a minute.

Advanced modeling techniques for system-level power integrity and EMC analysis

Abstract: In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, introducing new challenges to ensure the power integrity (PI) of the electronic systems, and increasing the electromagnetic interference (EMI). The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions and modeling techniques to assess and guarantee PI and electromagnetic compatibility (EMC) across the overall system that comprises the chip, package, and printed circuit board (PCB). Hence, PI and EMC/EMI are rapidly becoming a major concern for high-speed circuit, package, and board designers. In this work we investigate the impact of the chip power rail noise on system PI and EMI, and we show that by reducing the power rail noise thus assuring the system PI, it is possible to significantly reduce the electromagnetic (EM) conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and PCB designers to predict the power integrity and the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

Partial uniplanar compact electromagnetic bandgap combined with high-impedance surface to suppress simultaneous switching noise

Abstract: Proposed is a design for a partial uniplanar compact electromagnetic bandgap (UC-EBG) structure, in conjunction with a high-impedance surface (HIS), to suppress simultaneous switching noise (SSN) over the wide frequency range 0.38-15.494 GHz. Different from the conventional methods, which use an EBG plane, the proposed structure uses only two UC-EBGs at the excitation and receiving ports to suppress SSN. This technique can be applied to sensitive circuits to maintain their power integrity. The other region maintains good signal integrity when a signal return path is referenced to an EBG plane.

A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

Abstract: The package built-in three-dimensional distributed matching circuit[1], which had been developed for FCBGA , has been extended to the low-cost wire-bonding packages. The two-metal layer package designed for 6.4Gps SerDes (Serializer-Deserializer) achieved a ∼4dB return loss improvement as well as better signal waveform compared to the normal 50-Ohm design. In addition, signal-power coupling effect on the high-speed SerDes device has been analyzed for the first time based on the full-wave, full-3D, signal-power-combined electromagnetic analysis, which suggests that the power integrity design substantially affects the common mode noise generation inside the wire-bonding packages of high-speed SerDes devices.

Development of a practical electro-magnetic interference (EMI) simulation in high speed optical transceivers

Abstract: The growing bandwidth of optical communication systems has made great improvements to information technology infrastructures. However, electro-magnetic compatibility becomes an issue due to the high frequency of the components. EMI problems occur due to the miniaturization and high density of the Printed Circuit Board (PCB) mounted on the system. Generally, electro-magnetic radiation is generated by the circuit elements. For example, switching in the LSI raises the voltage swing between the power source and ground which is known as “ground bounce”. EMI problems related to the ground and power source are linked to the power integrity, and is influenced by the structure of the patch antenna parasitically existing between the power source and ground. That is to say, most of the time this problem can be solved by utilizing the appropriate power source and ground pattern layout at the PCB design stage. However, high speed digital signals measuring at more than 10 Gigabit per second (Gbit/s) typically have high frequency components in excess of 40GHz. There is little feasible knowledge available that illustrates guidelines for the perfect layout method to prevent the emission on the PCB for such a high frequency application. Therefore, we focused on the Finite Element Method used in the 3D electromagnetic field analysis simulator so that we could solve the emission within the frequency domain. We first correlated both qualitatively and quantitatively the actual measurements and the simulation results. Then we investigated the countermeasure for the emission intensity (EMI level) from the 10 Gbit/s optical transceiver by simulation and then verified it.

Power integrity optimization of 3D chips stacked through TSVs

Abstract: On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.

Signal/power integrity design strategy for low-cost package of high-speed memory I/O interfaces

Abstract: Based on the characteristic current on the stub series terminated logic (SSTL) topology, three design parameters, the effective power and ground inductance and the signal loop inductance, are proposed to evaluate on the performance of signal integrity (SI) and power integrity (PI) for the memory circuits. From these three parameters, a design flow systematically describes how to design the layout of package for the designers is presented. Using this design flow, an improved package, which refines from a real package substrate, are shown to have better performance of SI and PI under the condition of identical layout area. Finally, the chip-package co-simulation at time domain verified the validity of the design ideas.

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction

Abstract: Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on a high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing runtime instruction execution induced PDN resonance noise.

Impact of Photonic Crystal Power/Ground Layer density on power integrity performance of high-speed power buses

Abstract: This paper investigates the suppression of unwanted noise in high speed power buses by the adoption of Photonic Crystal Power/Ground Layer (PCPL) structure. The performance of PCPL with different densities of high dielectric rods is analyzed in terms of S-parameters and Electric field distribution. An attempt is made in order to relate geometrical properties (like rods' density and filling ratio) to the shift of the central frequency of the band gaps a well as bandwidth. The simulated results are validated by means of comparison with measured data.

Power integrity analysis and bypass capacitor selection using FDM on a printed circuit board

Abstract: Power delivery is a major challenge in present-day systems. This challenge is expected to increase in the next decade as systems become smaller and new materials are introduced into packages and boards. Planes form an integral part of a power delivery system (PDS). They provide charge to the switching circuits at high frequencies and support return current of the signal lines. Planes pairs are widely used on high-speed printed circuit boards. Planes are capacitive at low frequencies and become inductive at high frequencies. Since lateral dimensions of planes are multiple of λ, they behave as spatially distribute systems and resonate at higher frequencies due to the reflections from the open edges. The goal of this article is to approach an efficient numerical approach based on the finite difference method (FDM) to model the power/ground plane in a printed circuit board in frequency domain and how to choose decoupling capacitors for PDSs. The power system should meet the target impedance across a broad frequency range from direct current, up to the highest frequency of interest. To maintain the impedance of a PDS below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy.

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Abstract: Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.

Signal integrity simulation design of image processor PCB combined with electromagnetic compatibility analyses based on Altium Designer 6

Abstract: With the coming of the high-speed digital system age, signal integrity (SI) and electromagnetic compatibility (EMC) should not be ignored any more. In this paper, based on basic theories of SI and EMC, the high-speed digital design method for PCB using the SI simulation tool of Altium Designer 6 and EMC analyses is introduced, and the impedance control, power integrity (PI) design and SI (reflections and crosstalk) design of a piece of image processor PCB are demonstrated in detail. The simulation results show that the impedance control is perfect, reasonable termination can improve the waveforms and control the reflections and crosstalk.

GPGPU-based Latency Insertion Method: Application to PDN simulations

Abstract: With the progress of high-density integration technology of the circuits, a variety of signal and power integrity problems have become serious and important for the electronic design. This paper describes the fast circuit simulation by GPGPU-LIM (GPGPU-based Latency Insertion Method). First, LIM is reviewed, which is a fast algorithm. Next, implementation of LIM on the general purpose computing on graphic processing unit (GPGPU) is shown. Furthermore, this method is applied to the simulation of power distribution networks (PDNs). Finally, it is confirmed that GPGPU-based LIM is very practical and efficient for the large-scale PDN simulations.

Cavities' Identification Algorithm for Power Integrity Analysis of Complex Boards

Abstract: The analysis and the design of the Power Delivery Network (PDN) is crucial in the real world of high-speed and high-performance on-board systems In this context, the Cavity Model (where facing portions of power bus are considered electromagnetic resonant cavities) can be used to study the generation and propagation of noise Given a real-world board's layout, one of the primary requirements for the application of this technique is the geometrical identification of all the cavities and their connectivity This paper is focused on the fully automatic generation of this geometrical dataset as part of an integrated tool for the analysis and design of PDN

Modeling of IC power supply and I/O ports from measurements

Abstract: This paper addresses the generation of behavioral models of digital ICs for signal and power integrity simulations. The proposed models are obtained by external port measurements and by the combined application of specialized state-of-the-art modeling techniques. The proposed approach is demonstrated on the I/O buffers and the core power supply ports of a commercial 90nm flash memory.

Examining the Impact of Split Planes on Signal and Power Integrity

Abstract: Power and/or ground splits and slots frequently arise in real-world boards to manage the various constraints placed on the board designer. As a consequence, signal traces can often be forced to cross these plane split and slot boundaries or routed in close proximity to them. These trace routes may have a number of undesirable consequences on both signal integrity and power integrity. In this paper, we will examine the impact of split and slotted planes using both measured and simulated data.

Analysis of SMT decoupling capacitor placement in electronic packages using hybrid modeling method

Abstract: An efficient hybrid modeling method is presented for analysis of the surface-mount technology (SMT) decoupling capacitor placement in the power distribution network (PDN) of an electronic package. The PDN includes the multilayered power-ground (P-G) planes, the P-G vias, and the decoupling capacitors to provide a low-impedance path between the printed circuit board and the die. The SMT decoupling capacitors are commonly used to mitigate the resonant phenomenon of the electronic package in cavity-like structure and provide the additional return paths for the signal traces. Applying the modal decomposition of the waves propagating inside the P-G planes and the traces, the electro-magnetic fields can be decomposed into the parallel-plate mode and the transmission-line mode. The former is analyzed by using the scattering matrix method for the finite P-G planes with multiple vias. The multiconductor transmission-line theory is applied to model the micro-striplines and striplines in the package. The method has been experimentally validated.

Design of low cost QFP packages for multi-gigabit memory interface

Abstract: The feasibility of implementing a 3.2Gb/s XDR™ memory interface using an ultra low-cost LQFP package is analyzed. The target application includes multimedia electronics such as set-top boxes and HDTVs. Due to the large inductance of the LQFP package leadframes, power integrity is a major challenge for achieving high data rates. While single-ended signaling systems such as DDR and GDDR are very difficult to operate at multi-gigabit data rates using this highly inductive LQFP package, differential signaling systems such as an XDR memory interface is more immune to supply noise and it is suitable for high data rate operations. In this paper, we demonstrate that the XDR memory system with LQFP memory controller package can operate reliably at 3.2Gb/s. The proposed design is achieved by deploying a package/chip co-design approach, and by carefully balancing the supply-noise-induced jitter on different supply rails of the chip. Finally, the system function is validated under a test system with the proposed LQFP package and the model to hardware correlation at system level is presented.