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Showing papers on "Power integrity published in 2011"


Proceedings Article
01 Jan 2011
TL;DR: An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μV voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype as discussed by the authors.
Abstract: An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μV voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

42 citations


Journal ArticleDOI
TL;DR: An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μ V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype as mentioned in this paper.
Abstract: An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 μ V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

41 citations


Proceedings ArticleDOI
07 Apr 2011
TL;DR: A channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter is presented and tri-mode clocking is addressed to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.
Abstract: Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization [1–3]. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.

31 citations


Journal ArticleDOI
TL;DR: In this paper, a new concept based on power transmission line (PTL) is proposed to supply power, improve signal and power integrity, and enhance chip-to-chip communication speed.
Abstract: The performance of a system depends heavily on the communication speed between integrated circuits. One of the most important bottlenecks that limit the communication speed is simultaneous switching noise (SSN). A major contribution to SSN is return path discontinuities, which are caused by the change or disruption in return currents due to via transitions, aperture effects, etc. In this paper, a new concept based on power transmission line (PTL) is proposed to supply power, improve signal and power integrity, and enhance chip-to-chip communication speed. The first demonstration of constant current PTL (CCPTL)-based single-ended signaling scheme is implemented and measured. The results show that the CCPTL scheme improves the quality of the received signal in terms of voltage and timing margin.

25 citations


Proceedings ArticleDOI
05 Jun 2011
TL;DR: This paper proposes systemic decoupling capacitance optimization strategies that optimally balance between switching and rush current noises, and tradeoff between power integrity and wake-up time, hence power saving and proposes a novel re-routable decoupled capacitance concept to break the tight interaction between power Integrity and power saving.
Abstract: Power gating is essential for controlling leakage power dissipation of modern chip designs. However, power gating introduces unique power delivery integrity issues and tradeoffs between switching and rush current (wake-up) supply noises. In addition, in power-gated power delivery networks (PDNs), the amount of power saving intrinsically trades off with power integrity. In this paper, we propose systemic decoupling capacitance optimization strategies that optimally balance between switching and rush current noises, and tradeoff between power integrity and wake-up time, hence power saving. Furthermore, we propose a novel re-routable decoupling capacitance concept to break the tight interaction between power integrity and power saving, providing further improved tradeoffs between the two. Our design strategies have been implemented in a simulation-based optimization flow and the conducted experimental results have demonstrated significant improvement on leakage power saving through the presented techniques.

21 citations


Journal ArticleDOI
TL;DR: In this article, a double-sided silicon interposer for low impedance power delivery is presented for power ground planes in inhomogeneous dielectrics with conductive subsections using the multi-layered finite difference method (M-FDM).
Abstract: A novel double sided silicon interposer for low impedance power delivery is presented. In this letter, a model for power ground planes in inhomogeneous dielectrics with conductive subsections using the multi-layered finite difference method (M-FDM) is presented. Benefits of the silicon interposer in mitigating signal integrity issues arising due to return path discontinuities (RPDs) are also discussed for the first time along with a comparison to glass interposer.

20 citations



Proceedings ArticleDOI
16 May 2011
TL;DR: The results show that DVFS guarantees higher energy savings than clock gating, and improves the system performance by a factor of 3 when considering power consumption, improving hardware robustness to soft errors related to power integrity phenomena.
Abstract: This paper presents the study of Dynamic Voltage and Frequency Scaling (DVFS) technique applied to an existing multi-core architecture composed of 9 computational nodes interconnected by a hierarchical Network-on-Chip. The architecture was synthesized and characterized in area/power utilizing 65nm standard cell technology. For the analysis of the achievable energy/power saving, a representative algorithm from wireless communications was utilized as test case. Energy and power reduction results achieved with DVFS were then compared to the ones obtainable via clock gating. The results show that DVFS guarantees higher energy savings than clock gating. Moreover, when considering power consumption DVFS improves the system performance by a factor of 3 when compared to clock gating, improving hardware robustness to soft errors related to power integrity phenomena.

13 citations


Journal ArticleDOI
TL;DR: A fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network, and is shown to be very efficient for modeling of networks with very large numbers of nodes.
Abstract: Process scaling in modern integrated circuits has led to multiple signal and power integrity issues. In particular, ensuring reliable performance of on-chip power delivery systems has become a major design challenge. Rigorous analysis and simulations are required at the design stage to ensure proper functionality of an on-chip power supply. This puts a strain on existing numerical tools due to the sheer size of the power grids. In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the steady-state analysis of large-scale circuits, such as on-chip power distribution network. The proposed method is shown to be very efficient for modeling of networks with very large numbers of nodes. The comparison with one of the well-established methods used for the power grid analysis today, the Random-Walk algorithm, shows that LIM is almost two orders of magnitude faster.

13 citations


Proceedings ArticleDOI
10 Oct 2011
TL;DR: In this article, a new signaling scheme is proposed to address the issues associated with the power transmission line (PTL) and yield a significant improvement in signal integrity in high-speed systems.
Abstract: Power integrity has become an indispensable part to ensure signal integrity in high-speed systems. Simultaneous switching noise (SSN) in the power delivery network (PDN) is now one of major factors to place the limit on the noise margin for off-chip communication so that a great emphasis is being placed on controlling SSN. A power transmission line (PTL) has been suggested as a new PDN design to achieve near-zero SSN. In this paper, a new signaling scheme is proposed to address the issues associated with the PTL, and yield a significant improvement in signal integrity.

12 citations


Journal ArticleDOI
TL;DR: This paper tries to gather the Power Distribution Network techniques used to preserve power integrity in PCB designs when transmitting data rates over 6 Gbps using the newest commercial optical modules.
Abstract: This paper tries to gather the Power Distribution Network (PDN) techniques used to preserve power integrity in PCB designs when transmitting data rates over 6 Gbps using the newest commercial optical modules The PDN design described allows for proper impedance control of the power supply with the appropriate choice of the number, location and values of capacitors This method needs the knowledge of the electrical RLC model of the regulators, copper planes, capacitors and vias used in the PCB A particular case of PDN design will be presented for a module using one SNAP12 optical transmitter and one receiver connected to an Altera Stratix II GX FPGA This board is designed to work with data rates up to 75 Gbps for a high- energy physics application

Proceedings ArticleDOI
10 Oct 2011
TL;DR: In this paper, a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies is presented, where a lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current.
Abstract: This paper presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post data-processing procedure is introduced to separate and obtain the parameters of multiple current components. The results obtained by the proposed method are validated with other approaches.


Proceedings ArticleDOI
12 Dec 2011
TL;DR: This work presents a compression strategy aimed at representing the dynamic behavior of the structure through few carefully selected “basis functions”, and shows that model accuracy can be traded for complexity, with full control over approximation errors.
Abstract: Rational macromodeling via Vector Fitting algorithms is a standard practice in Signal and Power Integrity analysis and design flows. However, despite the robustness and reliability of the Vector Fitting scheme, some challenges remain for those applications requiring models with a very large port count. Fully coupled signal and/or power distribution networks may require concurrent modeling of hundreds of simultaneously coupled ports over extended frequency bands. Direct rational fitting is impractical for such structures due to a large computational cost. In this work, we present a compression strategy aimed at representing the dynamic behavior of the structure through few carefully selected “basis functions”. We show that model accuracy can be traded for complexity, with full control over approximation errors. Application of standard Vector Fitting to the obtained low-dimensional compressed system leads to the construction of a global state-space macromodel with significantly reduced runtime and memory consumption. Several benchmarks demonstrate the effectiveness of the approach.

Journal ArticleDOI
TL;DR: The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network.
Abstract: This paper addresses the generation of behavioral models of digital integrated circuits (ICs) for signal and power integrity simulations. The proposed models are obtained by external measurements carried out at the device ports only and by the combined application of specialized state-of-the-art modeling techniques. The present approach exploits a behavioral formulation, leading to models reproducing all the behavior of the IC ports as the input/output buffers and the core power delivery network. The modeling procedure is demonstrated for a commercial nor Flash memory in 90-nm technology housed by a specifically designed test fixture.

01 Jan 2011
TL;DR: A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance and Taguchi array optimization has been applied during the optimization process.
Abstract: System level signal integrity and power integrity problems for high speed serial links have been explored in this paper. An example of the USB 2.0 IP has been used in this paper, but the analysis is generic for all serial links. This paper considers signal and power integrity as effects simultaneoulsy. A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance. Sensitivity analysis is carried out with a set of dependent parameters affecting the performance. Taguchi array optimization has been applied during the optimization process. Finally, reflection gain concept is also applied to further improve the performance for the eye diagram. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc. Index Terms—Signal integrity, power integrity, serial links, bit error rate (BER), high speed data transmission

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this paper, the authors proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers of printed circuit boards (PCBs) for noise suppression and power integrity.
Abstract: Noise suppression and power integrity (PI) are two requirements for power/ground layers of printed circuit boards (PCBs) We have proposed the application of electromagnetic bandgap (EBG) structure and ferrite film to power/ground layers In this paper, not only a test board with the proposed structure but three other test boards to be compared were fabricated to measure with a vector network analyzer The measured data was evaluated for noise-suppression and PI characteristics Additional evaluation using a commercial circuit simulator was carried out to evaluate noise-suppression and PI characteristics, assuming a real power-supply circuit Through the evaluation, the test boards with ferrite film including the proposed structure provided sufficient results

Book
20 Jun 2011
TL;DR: This paper surveys the electrical and layout perspectives of SiP, and first introduces package technologies, and then presents SiP design flow and design exploration.
Abstract: The unquenched thirst for higher levels of electronic systems integration and higher performance goals has produced a plethora of design and business challenges that are threatening the success enjoyed so far as modeled by Moore's law. To tackle these challenges and meet the design needs of consumer electronics products such as those of cell phones, audio/video players, digital cameras that are composed of a number of different technologies, vertical system integration has emerged as a required technology to reduce the system board space and height in addition to the overall time-to-market and design cost. System-in-package (SiP) is a system integration technology that achieves the aforementioned needs in a scalable and cost-effective way, where multiple dies, passive components, and discrete devices are assembled, often vertically, in a package. This paper surveys the electrical and layout perspectives of SiP. It first introduces package technologies, and then presents SiP design flow and design exploration. Finally, the paper discusses details of beyond-die signal and power integrity and physical implementation such as I/O (input/output cell) placement and routing for redistribution layer, escape, and substrate.

Proceedings ArticleDOI
14 Mar 2011
TL;DR: This work proposes a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks and demonstrates the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods.
Abstract: Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worst-case operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods.

Proceedings ArticleDOI
15 Dec 2011
TL;DR: In this article, a Matlab tool is developed to identify problems prior to the final layout of a power distribution network, which can be used to identify the design flaws arising due to parasitic effects.
Abstract: The simulation and the analysis of a power distribution network (PDN), termed power integrity (PI), is performed in the frequency domain and primarily involves analyzing the power and ground planes, the decoupling capacitors and the simultaneous switching noise (SSN). The original layout is modified based on these PI analyses to account for any design flaws arising due to parasitic effects. To avoid an expensive procedure, it is add an additional simulation at the pre-layout stage to catch the major design flaws. These simulations are used to guide the final layout process. There are several commercial tools available to simulate a power distribution network. The goal is to develop a Matlab tool to perform about same functions as the commercial tools do, so it can be used to identify problems prior layout.

Patent
20 Jul 2011
TL;DR: In this paper, a novel ultra wide band electromagnetic band gap structure which belongs to the technical field of information is presented, which is mainly used for replacing a power layer of the traditional high speed circuit/microwave circuit so as to suppress ground bounce noise in the structures and realize better power integrity.
Abstract: The invention provides a novel ultra wide band electromagnetic band gap structure which belongs to the technical field of information. The structure is mainly used for replacing a power layer of the traditional high speed circuit/microwave circuit so as to suppress ground bounce noise in the structures and realize better power integrity. The structure has a typical three-layer circuit board structure comprising a dielectric layer in the middle and two metal layers up and down, wherein the electromagnetic band gap structure is arranged on the upper layer. In the invention, a typical example is verified, i.e. a sample prepared in an experiment is tested through a network analyzer, which confirms that the structure provided by the invention can realize noise suppression superior to -30dB to any two ports in a frequency range from 500MHz to 5.5GHz.

Proceedings ArticleDOI
03 Jul 2011
TL;DR: In this paper, it was shown that the reactive near fields radiating from openings within the EBG layer can be substantial and are present in the frequency band including propagating and non-propagating mode regions.
Abstract: Electromagnetic bandgap structures are frontrunners in solving GHz switching noise in printed circuit boards and packages. However, less attention has been given to whether or not the introduction of EBGs affect the EMI potential of the circuit to couple unwanted energy to neighboring layers or interconnects. In this paper, we show that the bandgap of EBG structures, as generated using the Brillouin diagram, does not necessarily correspond to the suppression bandwidth typically generated using S-parameters. We show that the reactive near fields radiating from openings within the EBG layer can be substantial and are present in the frequency band including propagating and non-propagating mode regions. These fields decay fast with distance, however, they can couple significant energy to adjacent layers and to signal lines. Based on this work, design guidelines for EBG structures can be drawn to insure not only suppression of switching noise but also minimization of EMI and insuring signal integrity.

Proceedings ArticleDOI
12 Dec 2011
TL;DR: In this article, the authors present analysis and quantification of the impact of RPDs in the presence of a power delivery network and provide designing and modeling guidelines to further improve computational efficiency.
Abstract: When the return path of a signal is not continuous, unwanted noise will couple to the return current, leading to worsening of the signal waveform. To prevent such a signal integrity issue, a thorough understanding of the physics of the return path discontinuity (RPD) is critical. This paper presents analysis and quantification of the impact of RPDs in the presence of a power delivery network. The study of the different types of RPDs, such as a gap between reference planes and an aperture, provides designing and modeling guidelines. The guidelines are applied to an efficient PDN analysis method to further improve computational efficiency.

Proceedings ArticleDOI
03 Nov 2011
TL;DR: This paper introduces a package of a high-speed and high-density switching ASIC with over 1000 pins and hundreds of high- speed transmission lines crowded in two layers of the substrate, and also demonstrates Signal Integrity (SI) and Power Integrity (PI) implementation.
Abstract: This paper introduces a package of a high-speed and high-density switching ASIC with over 1000 pins and hundreds of high-speed transmission lines crowded in two layers of the substrate, and also demonstrates Signal Integrity (SI) and Power Integrity (PI) implementation. In order to route the transmission lines with minimum distortion, crosstalk and attenuation, routing is co-designed with die and BGA maps. To guarantee that over a hundred transmission lines will be matched identically, each transmission line is designed to have a corresponding continuous return path routed among integrated copper shapes. Various routing schemes designed to take advantage of the physical and electrical performance of materials and structures are also implemented to optimize the performance of the transmission line. Various simulations are carried out on test segments to evaluate performance and signal integrity in the frequency and time domains.

Proceedings ArticleDOI
12 Dec 2011
TL;DR: The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.
Abstract: In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.

Journal ArticleDOI
TL;DR: This work proposes a novel approach to proactively suppress instruction loop induced PDN resonance noise at the runtime using a clock frequency actuator design to predict current load variation and proactively select an optimal clock frequency to suppress the resonance.
Abstract: Power delivery network (PDN) is a distributed resistance-inductance-capacitance (RLC) network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on the high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing instruction loop induced PDN resonance noise at the runtime.

Proceedings ArticleDOI
17 Oct 2011
TL;DR: In this paper, an analytical TSV model based on the MIS (Metal-Insulator-Silicon) structure analysis, TSV's electrical performances and their frequency and time-domain analysis in viewpoint of transmission line, and on-chip PDN impedance analysis depending on on chip PDN design including TSV arrangements and stacking configurations of 3D IC are addressed.
Abstract: In the paper, an analytical TSV model based on the MIS (Metal-Insulator-Silicon) structure analysis, TSV's electrical performances and their frequency- and time-domain analysis in viewpoint of transmission line, and on-chip PDN impedance analysis depending on on-chip PDN design including TSV arrangements and stacking configurations of 3D IC are addressed.

Proceedings ArticleDOI
12 Dec 2011
TL;DR: In this article, the authors used a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer, which improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω.
Abstract: Power integrity (PI) for recent electronics circuits and systems is the most important technological issue in the field and has been addressed in important papers through several approaches [1][2]. The latest concept of the best PI condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference(EMI) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16-channel 3 Gbps/pin I/O interface board in this study. Even though the simultaneous switching of two sets of 16 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the PI status can be verified by the condition. Result was that PIS structure kept better than Cu plane in the VDD fluctuation.

01 Nov 2011
TL;DR: In this paper, the authors introduced the concept of package-common-mode resonance, which is caused by a parasitic capacitance and parasitic inductances between package and PCB ground, which makes degradation of signal and power integrity.
Abstract: Package-common-mode resonance which is caused by a parasitic capacitance and parasitic inductances between package and PCB grounds makes degradation of signal and power integrity. A parasitic capacitance between a package ground and a PCB ground anti-resonates with a parasitic inductance at ground connections such as solder balls in a BGA package. In this resonance, currents flow on power and ground lines in the package with the same phase. Thus, the authors name this antiresonance “Package-common-mode resonance”. The package-common-mode resonance causes the power and/or ground bounce and increase of jitter of the output signal. According to measurement results of test boards, the resonance frequency is depend on the number of ground connection because the parasitic inductance is decreased by increasing ground connection. For example, the resonance frequency was changed from 575 MHz to 862 MHz in the test board when the number of the ground connection was decupled.

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this article, a physics-based equivalent circuit model of on-chip decoupling capacitor for chip modelling is proposed for use in accurate power integrity (PI) analysis, which can be easily applied to onchip decouple capacitor design based on the construction flow.
Abstract: A physics-based equivalent circuit model of on-chip decoupling capacitor for chip modelling is proposed for use in accurate power integrity (PI) analysis. The proposed model can be easily applied to on-chip decoupling capacitor design based on the construction flow. The accuracy of the model has been verified with circuit simulation. By using this model and an incomplete one, a case study of chip-package co-simulation in H-spice environment is investigated, which successfully demonstrate the purpose of the proposed model.