Showing papers on "Power integrity published in 2012"

Electrical Modeling and Design for 3D System Integration: 3D Integrated Circuits and Packaging, Signal Integrity, Power Integrity and EMC

Abstract: Based on the author's extensive research, this book sets forth tested and proven electromagnetic modeling and simulation methods for analyzing signal and power integrity as well as electromagnetic interference in large complex electronic interconnects, multilayered package structures, integrated circuits, and printed circuit boards. Readers will discover the state of the technology in electronic package integration and printed circuit board simulation and modeling. In addition to popular full-wave electromagnetic computational methods, the book presents new, more sophisticated modeling methods, offering readers the most advanced tools for analyzing and designing large complex electronic structures.

Interconnect design and analysis for Through Silicon Interposers (TSIs)

Abstract: The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this paper we describe the key electrical elements in a typical TSI digital system and discuss their impact on overall system performance. We also discuss the system level power integrity analysis for TSI as its power delivery is one of the major engineering challenges.

Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators

Abstract: Distributive on-chip voltage regulation is appealing to solving the power integrity problems in nowadays high-end SoCs. Nevertheless, ensuring the stability of large-scale power delivery networks regulated by a multiplicity of voltage regulators is challenging due to the size of the system and complex interactions between the regulators and the large loading network. We present a theoretically elegant framework that provides a rigorous guarantee for network stability. We further develop a practical design approach that largely decouples the design of linear voltage regulators from that of the complex load, making it feasible to ensure the stability of the complete network. The presented design approach has been successfully applied to several design examples with guaranteed stability and competitive performances.

Skin-effect model for round wires in PEEC

Abstract: In this paper we consider the skin- and radiation effects for a thin wire segment. Circuit models are being constructed which are suitable for the modeling of thin wires like the wire bonds. We use the internal-external inductance model for this purpose of including the skin-effect in the partial inductance. These models make it possible to include thin, round conductors in a PEEC model at a much lower cost in compute time. The ultimate goal is to construct a circuit model which can be applied both in the time and frequency domain to signal and power integrity problems.

A silicon-validated methodology for power delivery modeling and simulation

Abstract: Power integrity has become increasingly important for the designs in 32nm or below. This paper discusses a silicon-validated methodology for microprocessor power delivery modeling and simulation. There have been many prior works focusing on power delivery analysis and optimization. However, none of them provided a comprehensive modeling methodology with post-silicon data to validate the use of the models. In this paper, we present power delivery system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32nm industrial microprocessor design. Our models are able to capture the unique impacts of on-die inductance, state dependent coupling capacitance and die-package interaction. Those impacts happen to be prominent for the designs in 32nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for power delivery analysis. The impact of power delivery noise on timing margin was accurately estimated showing a good agreement to the worst-case jitter measurements.

Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs

Abstract: Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis.

Signal Integrity Analysis of High-Speed Interconnects by Using Nonconformal Domain Decomposition Method

Abstract: 3-D interconnect techniques in multilayer very large scale integration design, such as stacked layers and various chip-stacking systems, have paved the way for the improvement of integrated circuit density and operation speed. However, these techniques often accompany with impedance discontinuities that induce signal integrity (SI)/power integrity and electromagnetic interference effects. Consequently, SI analysis serves as one of the key guidelines of chip-package-board design in deep submicrometer technology. However, full-wave numerical analysis of 3-D high-speed and high-density interconnects is also considered to be a great challenge. In this paper, a nonconformal domain decomposition method with second-order transmission condition for SI analysis of high-speed interconnects on a multiscale multilayer printed circuit board is presented. The accuracy and robustness of the proposed method are first witnessed by modeling a six-layer two-trace differential pair. Then we study a 14-layer 16-trace interconnect model to demonstrate the efficiency of the method. Eye diagrams of the two models are also presented in the time-domain SI analysis.

Power Integrity and Shielding Effectiveness Modeling of Grid Structured Interconnects on PCBs

Abstract: In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB) We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation The model includes an equivalent circuit model of fringing capacitance and probing ports The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms

Abstract: Swarm intelligence is applied to a module of high speed system design problem. To maintain power integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances' peaks is presented. The optimal values and the optimal positions of the decoupling capacitors are found using three different swarm intelligence methods - particle swarm optimization, cuckoo search method and firefly algorithm. Optimum values and locations of decoupling capacitors are obtained, by which anti-resonances' peaks of loaded board are minimized.

Signal integrity: Efficient, physics-based via modeling: Integration of striplines

Abstract: In the first article of this series, principles and methods of physics-based via modeling were discussed. It was shown how the electromagnetic behavior of vias can be captured by an equivalent circuit based modeling approach that describes all relevant full-wave effects. In this follow-up article, the authors present an approach to integrate striplines into the physics-based via model. The striplines can be located at any layer of the stackup and they may constitute both single and multiconductor transmission lines. The integration of striplines extends the via representation to a full, efficient interconnect model of, for instance, printed circuit board signal links. An intuitive integration approach at a circuit simulator level and application examples are discussed in this article as well.

Macromodeling of complex power delivery networks for efficient transient simulation

Abstract: Simulation of power delivery networks has been traditionally done in the frequency domain, assuming a linear noise source represented by a Thevenin current source. As the technology progresses, power integrity needs to be maintained in spite of lower noise requirements with decreasing supply voltages below 1 V; and increasing current consumption. Hence more accurate simulation methodologies that take into account the non-linear behavior of ICs are becoming necessary. Transient simulation of a complex power delivery network in the presence of non-linear elements using SPICE is however computationally prohibitive. Hence, development of new efficient methodologies is critical for power integrity design in the time domain. In this paper, we use vector fitting to create a macromodel of a power delivery network by first calculating its frequency response. The generated macromodel is much smaller than the original power delivery network model, hence the efficiency is greatly improved. The macromodel needs to satisfy the property of passivity as in the original model. We present a new methodology to create guaranteed passive macromodels by construction.

Signal Integrity and Power Integrity Issues at System Level

Abstract: System-level signal integrity (SI) and power integrity (PI) problems are taken into account. System-level simulation of high-speed systems with effect of external environment is described. SI and PI issues with complete analysis of package, board, termination, squid card, and decoupling network are shown. Common problems of simulations-passivity violation, stability, causality, and interoperability, are also discussed.

Effects of critically damped total PDN impedance in chip-package-board co-design

Abstract: As CMOS LSIs operate at higher clock frequency and at lower supply voltage, power integrity is becoming a critical issue to maintain digital electronic systems more stable. Power supply fluctuation excited by core circuits or I/O circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN due to the parallel combination of on-chip capacitance and package inductance induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by designing different on-chip PDN properties. The measured power supply noises for the four test chips successfully showed typical characteristics of 3 different regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on a chip.

Signal integrity: Efficient, physics-based via modeling: Principles and methods

Abstract: This article discusses the high-frequency behavior of thru-hole vias enclosed by solid reference planes in packages and printed circuit boards and reviews some efficient modeling alternatives for signal and power integrity applications. The electromagnetic behavior of vias, including the excitation of parallel-plate modes and the role of return vias, is introduced as preamble to the modeling approaches. The physics-based via model and its building blocks are then discussed. The last section reviews some improvements to the via model, covering intrinsic models for the near field of vias and the utilization of contour integral and multiple scattering methods.

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization

Abstract: To maintain Power Integrity in a high speed system, an effective methodology for suppressing the cavity-mode anti-resonances peaks is presented. The optimum values and the optimal positions of the decoupling capacitors are found using Particle Swarm Optimization, which leads to optimum impedance of power plane loaded with decoupling capacitors. Optimum number of capacitors and their values, by which impedance of loaded board is matched below the target impedance of the system, are found.

Power integrity design tips to minimize the effects of mounting inductance of decoupling capacitors

Abstract: The simulation and the analysis of a power distribution network (PDN), termed power integrity (PI), are performed in the frequency domain and primarily involve analyzing the power and ground planes and the decoupling capacitors. The capacitors provide a temporary source of localized energy for instantaneous current demands from a IC, and a low-impedance return path for high frequency noise. Capacitors need to be close to the device to perform the decoupling function. Efficient energy transfer from the capacitor to the integrated circuit requires placement of the capacitor at a fraction of a quarter wavelengths of the IC's power pins. The purpose of this paper is to simulate a four layer PCB, with power/ground planes, to evaluate the effectiveness and the importance of decoupling capacitors placement, using tools and methodologies to determine the important factors like performance, cost and board area.

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction

Abstract: Power supply noise has become one of the primary concerns in low power designs To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical design methodologies have been adapted, which may bring significant design overhead In view of this, various runtime techniques have been proposed in literature to suppress power grid noise adaptively This paper first presents various challenges in power grid designs from an industrial perspective, explains the difficulties in handling them at deign time, and then reviews various runtime techniques to adaptively suppress power supply noise, including sensor-based power gating, re-routable decaps, proactive clock frequency actuator, and PLL based clocking

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)

Abstract: Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. To enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to deliver power/ground signals to different layers, must be carefully placed to minimize IR-drop. However, the currents in 3D ICs are not deterministic and exhibit both spatial and temporal correlations. In view of this, we propose a correlation based heuristic algorithm for P/G TSV placement. Unlike most existing works, the proposed algorithm does not need iterations of full-grid simulations. Thus, it is especially attractive for large designs with millions of nodes. Experimental results on TSMC 90nm industrial designs indicate that the proposed method can achieve up to 70% reduction in IR-drop compared with the current industry practice, which uniformly distributes P/G TSVs.

Power and signal integrity co-design for quad flat non-lead package

Abstract: The co-design of power and signal integrity issues on a quad flat non-lead (QFN) package is described. A novel decoupling capacitor is achieved by separating the die pad and footprint, coating a solder mask on the footprint and connecting the footprint to the printed circuit board power plane through a via. Large capacitance between power (footprint) and ground (die pad) resulted from the thin mask and large die pad lowering the input impedance of the power delivery network without parasitic effects at low frequency. A power bridge and a ground bridge are introduced to substitute the wire bond to decrease the inductance and hence the impedance magnitude up to 30%, thus enhancing the power integrity at high frequency. A modified design called hybrid power/ground exhibits great signal integrity by providing good reference for signals. The thermal dissipation is also better than the first design through direct contact of the die pad and the footprint ground regions. The overall design demonstrates excellent broadband performance for signal and power integrity.

Insertion of parallel RL circuits into power distribution network for simultaneous switching current reduction and power integrity

Abstract: We investigated a method using parallel RL circuits inserted into power distribution network (PDN) of integrated circuits (ICs) to enhance the IC in EMI and PI performance. Optimal damping resistances of the parallel RL circuit were derived from a characteristic equation of an equivalent circuit of a partial PDN that contributed to PDN resonances dominantly. The parallel RL circuit with the optimal resistances damps the PDN resonances as quickly as possible and reduces peaks in simultaneous switching current that will cause EMI and in input impedance of PDN related to PI. We validated the parallel RL circuit with respect to EMI and PI performance of ICs numerically and experimentally. Results of these validation showed that the proposed method descend the simultaneous switching current at both chip-package-board and on-board resonant frequency. It is also confirmed that insertion of the parallel RL circuits into the power trace reduced the impedance peak due to the chip-package-board resonance.

Switching-current measurement for multiple ICs sharing a common power island structure

Abstract: Switching currents in active integrated circuits (ICs) generate noise in the power distribution network (PDN), which is one of the main sources for many signal/power integrity and electromagnetic interference issues in high-speed electronic devices Accurate knowledge of the switching currents is the key to ensure a good PDN design This paper proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage

Power integrity analysis of TSV based 3-D integrated circuits

Abstract: The power supply grids of integrated circuits (ICs) are interconnected through silicon vias (TSVs) to form a 3-D chip integration in vertical direction. The required currents for each functional device to operate in the ICs are supplied through power and ground TSV pairs and power distribution meshes. Accurate estimation of power/ground noises (static and dynamic drops) in a 3-D power distribution network is crucial for a robust power supply design in order to operate the devices functionally. With fast switching characteristics of the devices, the worst case power supply noise may not be analysed accurately. In this paper, we present a systematic approach to analyse the static and dynamic drop, as a function of switching time, in power supply grids of 3-D ICs. Furthermore the approach is extended to investigate noise sensitivity of TSVs and power supply grids with decoupling capacitors.

A signal and power integrity oriented packaging for low cost and high performance systems

Abstract: A packaging strategy utilizes high-dielectric ultra thin film between power and ground planes is presented High-dielectric ultra thin film between power and ground planes is used not as an embedded capacitor but a low impedance power distribution route directly connected to the chip The package has a ground plane in the uppermost layer and power plane in the next metal layer in order to eliminate inductance of vias, and low ESL capacitors are mounted on the surface Test four-layer organic interposers of 15 mm square were fabricated for a feasibility study of this packaging strategy As a result it is demonstrated that this structure greatly reduces PDN impedance in higher frequencies and the effectiveness using high-speed CMOS differential drivers

Substrate noise suppression technique for power integrity of TSV 3D integration

Abstract: In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.

Framework for co-simulation of signal and power integrity in server systems

Abstract: Considerations for comprehensive simulation and analysis of high-speed links in complex server systems are discussed in this work. A framework that considers the interactions between multiple signals and the power distribution network is described. In the last section, the nature of the interactions between power and signal domains is analyzed by means of a simplified scenario at board level.

Domain and modal decomposition for efficient signal and power integrity analysis of multilayer packages and PCBs

Abstract: This paper systematically explores the underlying principle of a special domain and modal decomposition approach, and reports its latest advancement in modeling and simulation of multilayer packages and printed circuit boards for signal and power integrity analysis. Simulation results by different numerical techniques encompassed in the domain and modal decomposition approach are compared against those from measurement and full-wave simulation. The special domain and modal decomposition approach, compared with full-wave methods, exhibits faster simulation speed with good accuracy.

System power integrity impact by package power/ground balls assignment and decoupling capacitors

Abstract: Power integrity is one of the important issues of system design. Power and current levels are expected to increase with a corresponding to decrease in the voltage and increment of I/O number. Based on these factors, system designer faces the challenge on power delivery network. The power/ground (P/G) ball is often used as a link between the package and printed circuit board (PCB). It relates to the system power distribution from the voltage regulator module (VRM) to IC. When considering the power delivery network (PDN) design, power/ground balls position is the key point for complete power delivery. In this research, the assignment of the power/ground balls at different places and improvement of resonance impedance with different decoupling capacitors have been investigated for the impact of power integrity. The proposed arrangement of power/ground balls position is presented. The parasitic effects for different conditions of system design are extracted for comparison. The simulation results confirm with our theoretical analysis.

Modeling and design of an ultra-miniaturized WLAN sub-system with chip-last embedded PA and digital dies

Abstract: System integration by die-embedding within electronic packages offers significant advantages in miniaturization, cost and performance for mobile devices. This paper presents the functional design and analysis of ultra-thin packages that combine embedded actives (GaAs Power Amplifier and a baseband digital IC) with embedded passives (band-pass filters), leading to an ultra-miniaturized WLAN sub-system. This chip-last design routes embedded dies in the outer build-up layer, using Embedded MEMS Actives and Passives (EMAP) technology being developed in the Georgia Tech PRC's industry consortium, as an alternative, lower cost approach over current chip-first and chip-middle methods. Electromagnetic (EM) simulations were performed in order to tune the electrical performance of interconnections based on die specifications and package configuration. The digital package was designed with multiple power-ground pair islands to enhance noise isolation, while improving overall signal and power integrity. The embedded module designs for RF transmitter and the baseband IC measure at 2.8mm × 3.2mm × 0.25mm and 10mm × 10mm × 0.25mm respectively, achieving over 4.5× volume reduction compared to existing wire-bond packages.

I/O supply current synthesis for power integrity analysis of single-ended signaling scheme

Abstract: The simultaneous switching noise (SSN) from single-ended signaling I/O interfaces is significant when there are multiple channels transmitting data in parallel. The memory interfaces use the single-ended signaling scheme where the power delivery noise spectrum may coincide with some critical radio bands or resonance frequencies within the platform depending on the bit pattern being transmitted from the driver buffers. This will adversely affect the timing margin and can be one of the electromagnetic interference (EMI) sources as well. While it is good to use transistor buffer models in SSN estimation, it may significantly increase the complexity resulting in too long simulation time or convergence problems. The suggested method takes the transient supply currents when the transistor buffer transits its state from 0 to 1 and from 1 to 0, and synthesizes the full supply current for an arbitrary bit-pattern and data rate. This allows high accuracy in the supply current profiles while minimizing the power integrity simulation complexity. The method is extendable to tri-state buffers and different channel termination schemes.