Showing papers on "Power integrity published in 2013"

Modeling and Application of Multi-Port TSV Networks in 3-D IC

Abstract: Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs) While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them In this paper, we develop a simple yet accurate circuit model for a multiport TSV network (eg, coupled TSV array) by decomposing the network into a number of TSV pairs and then applying circuit models for each of them We call the new model a pair-based model for the multiport TSV network It is first verified against a commercial electromagnetic solver for up to 20 GHz and subsequently employed for a variety of examples for signal and power integrity analysis

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

Abstract: In this paper, we present a transient modeling of electromigration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs. In particular, we model atomic depletion and accumulation, effective resistance degradation, and full chip-scale PDN lifetime degradation due to EM. Our major focuses are on: (1) time-dependent multi-physics EM modeling approach to model TSVs and connecting wires under the influence of coupled physical phenomenon including electric field, temperature, and stress; (2) time-dependent EM-aware power integrity analysis methodology, which is integrated with the TSV modeling approach to predict long-term IR-drop degradation in full-chip 3D power delivery networks. Our studies show that voids and hillocks grow at various TSV-to-wire interfaces and degrade the effective resistance of TSVs significantly. In addition, our full-chip PDN lifetime analysis shows significant increase in maximum IR drop during lifetime due to EM effects.

Eagle-eye: a near-optimal statistical framework for noise sensor placement

Abstract: The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume, either implicitly or explicitly, that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. In this paper, we formally define the problem of noise sensor placement along with a novel sensing quality metric (SQM) to be maximized. We then put forward an efficient algorithm to solve it, which is proved to be optimal in the class of polynomial complexity approximations. Experimental results on a set of industrial power grid designs show that compared with a simple average-noise based heuristic and two state-of-the-art temperature sensor placement algorithms aiming at recovering the full map or capturing the hot spots at all times, the proposed method on average can reduce the miss rate of voltage emergency detections by 7.4x, 15x and 6.2x, respectively.

Design and modeling for 3d ics and interposers

Abstract: System Integration and Modeling Concepts Modeling of Cylindrical Interconnections Electrical Modeling of Through Silicon Vias Electrical Performance and Signal Integrity Power Integrity, Return Path Discontinuities and Thermal Management.

Selection and placement of decoupling capacitors in high speed systems

Abstract: The Power Integrity problem for high speed systems is discussed in context of selection and placement of decoupling capacitors. Power Integrity is maintained by damping the cavity mode peaks at resonant frequencies using decoupling capacitors. This article focuses on damping cavity mode effects in power delivery networks by the particle swarm optimization technique. The s-parameter data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their locations on the board are found using the presented methodology, which can be used for similar power delivery networks in high speed systems.

A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

Abstract: This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve significant challenges with receiver input and transmitter output insertion loss, power integrity, ESD, and reliability. The transceiver clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The receiver front-end utilizes a 3-stage CTLE with wide input common-mode to remove the post-cursor ISI. The CTLE is fully adaptive using an LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The transceiver achieves BER 10-15 at 6.6 Gb/s over a 20 dB loss channel. Power consumption is 129 mW from 1.2 V and 1 V supplies.

A new approach to power integrity with thinfilm capacitors in 3D IPAC functional module

Abstract: This paper presents a new active and passive integration concept called 3D IPAC (Integrated Actives and Passives) to address the power integrity in high-performance and multifunctional systems. The 3D IPAC consists of an ultra-thin glass module with through-vias and double-side integration of ultra-thin active and passive components to form functional modules. By integrating power ICs, storage capacitors and inductors, and high-frequency decoupling capacitors in ultra-thin (30-100 μm) glass substrates, 3D IPAC Voltage Regulator Module (3D IPAC VRM) provides a complete and ultra-miniaturized solution to power integrity. The ultra-thin 3D IPAC allows both actives and passives very close to each other and to the other active dies, resulting in improved performance over conventional SMDs and state-of-art IPDs for decoupling functions. The first part of the paper presents modeling results to show the benefits of the 3D IPAC module as a power integrity solution. The second part of the paper presents the fabrication and characterization of high-k thinfilm capacitors and etched aluminum film capacitors integrated on either sides of a through-via 3D IPAC glass substrate. This paper, therefore, demonstrates the integration of heterogeneous capacitors on a single ultra-thin glass substrate for the first time, and presents its benefits as a complete solution for power integrity.

Power-pulsing schemes for vertex detectors at CLIC

Abstract: The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector (?

System level signal and power integrity analysis for 3200Mbps DDR4 interface

Abstract: For single-ended signaling DDR4 channels at 3200Mbps, signal and power integrity issues become increasingly challenging with much smaller voltage and timing windows to balance the budget. As systems increase data rate and IO count, supply noise does not scale accordingly. We present a system level signal and power co-simulation analysis to optimize system performance under stringent timing requirement [1]. Signal integrity of DDR4 interface, such as inter-symbol interference ISI, reflection, and signal cross talk, needs to be minimized in order to meet an ever shrinking timing budget. Also, power delivery network (PDN) design becomes very difficult as a result of smaller die size and multilayer complex package design. SI and PI co-design optimization is driven by both channel performance and overall system cost.

Selective Glitch Reduction Technique for Minimizing Peak Dynamic IR Drop

Abstract: This paper proposes a glitch co mpensation technique which involves reducing glitch power in selected combinational cells to reduce peak current which contributes to dynamic voltage or IR drop. The proposed methodology can be seamlessly integrated to existing physical design flo ws. A glitch is an undesired transition that occurs before intended value in dig ital circuits. A glitch occurs in CMOS circu its when d ifferential delay at the inputs of a gate is greater than inertial delay, which results into increased gate switching and hence notable amount of power consumption. When such large nu mber of logic gates switch close to the same t ime they will contribute to power integrity challenge called pe ak dynamic IR drop. The glitch power is becoming more pro minent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and dynamic power. In the proposed methodology we are using transmission gate as a compensation circuit to reduce extra leakage and dynamic power. A flo w is proposed for charactering the pass transistor logic to cater different delay values. The proposed methodology has been validated on a plac e and routed Multiply Accumulate (MA C) layout imp lemented using Synopsys SAED 9 0n m Generic library. Experimental results show 12% to 50% reduction in top 10 peak transient IR drop numbers with just 12% g litch power reduction in selected combinational cell instances. When compared to traditional on-chip decoupling capacitor (Decap) cells insertion method the proposed technique could reduce the peak IR drop numbers by the same amount with just 5% increase in total core capacitance.

Optimization of 3D stack for electrical and thermal integrity

Abstract: Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.

Latency Insertion Method (LIM) for Electro-Thermal Analysis of 3-D Integrated Systems at Pre-Layout Design Stages

Abstract: In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. Application of the method to the problems specific to the early pre-layout design stages is considered. This method can be particularly useful for the early tradeoff and feasibility studies of on-chip and off-chip interconnect systems as well as of entire chip and package structures. The proposed method is shown to be suitable for modeling of both electrical and thermal phenomena occurring in high-speed high-performance very large scale integration circuits at the pre-layout design stages. Capability of the LIM to perform steady state and transient thermal analysis of a 3-D integrated circuit model is demonstrated with an example derived from an actual industry design. The experiments carried out in this paper demonstrate that the proposed methodology significantly outperforms conventional computer-aided design tools.

Power integrity analysis for core logic blocks

Abstract: In this paper, the new framework for power integrity analysis for core logic blocks is presented. Balancing on-chip timing budget becomes more challenging as both data and clock jitter increase due to large power noise. Conventional power integrity (PI) analysis focuses on reducing supply noise and does not provide timing jitter information. This paper proposes a general framework to model timing jitter due to supply noise. The proposed methodology can be used to define power distribution network (PDN) design requirements. This timing-based PDN design leads to significant reduction in the pessimism associated with either conventional target impedance concept, or static or dynamic power integrity analysis.

IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications

Abstract: Modern IC power delivery systems encompass large on-chip passive power grids and active on-chip or off-chip voltage converters and regulators. While there exists little work targeting on holistic design of such complex IC subsystems, the optimal system-level design of power delivery is critical for achieving power integrity and power efficiency. In this article, we conduct a systematic design analysis on power delivery networks that incorporate Buck Converters (BCs) and on-chip Low-Dropout voltage regulators (LDOs) for the entire chip power supply. The electrical interactions between active voltage converters, regulators as well as passive power grids and their influence on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level codesign of a complete power delivery network is facilitated by a proposed automatic optimization flow in which key design parameters of buck converters and on-chip LDOs as well as on-chip decoupling capacitance are jointly optimized. The experimental results demonstrate significant performance improvements resulted from the proposed system cooptimization in terms of achievable area overhead, supply noise and power efficiency. Impacts of different decoupling capacitance technologies are also investigated.

SoC power integrity from early estimation to design signoff

Abstract: Summary form only given. Power integrity has become a major integration challenge even for low power ARM-based SoC design. As performance requirements demand higher speed, more advanced process nodes reduce transistor level voltage margin, and low power consumption dictate aggressive power saving schemes such as more frequent power mode shifts and power gating, it's challenging to satisfy the power integrity requirements. Following descriptions are some important aspects for SoC chip design.

Effect of aging on power integrity of digital integrated circuits

Abstract: Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity of digital integrated circuits and clarifying its origin. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip are combined with electric stress to characterize the influence of aging on power integrity. Simulation based on ICEM modeling modified by an empirical coefficient in order to take into account the circuit aging is proposed to model the evolution of the power integrity induced by device aging.

Study of EMC optimization of automotive electronic components using CAE

Abstract: As more vehicles become equipped with advanced electronic control systems, more consideration is needed with regards to automotive safety issues related to the effects of electromagnetic waves. Unwanted electromagnetic waves from the antenna, electricity and other electronic devices cause the performance and safety problem of automotive components. In general, Power Integrity and Signal Integrity analysis have been widely used, but these analyses have stayed PCB level. PCB base analysis is different from radiated emission TEST condition so its results are used just for reference. This paper propose EMC optimization technology using module level 3-dimensional radiation simulation process closed to fundamental test conditions. If module level EMC analysis, which is proposed in this study, is applied to all automotive electronics systems, unexpected EMC noise will be prevented.

A novel EBG structure with super-wideband suppression of simultaneous switching noise in high speed circuits

Abstract: A novel uniplanar electromagnetic band-gap structure to maintain power integrity by suppressing simultaneous switching noise (SSN) is presented. The EBG structure with stopband from 750 MHz to 5.10 GHz is designed, fabricated and validated using network analyzer. Simulation results are verified by measurements and compared with the earlier published structures. Suppression of resonant cavity modes of power plane by EBG structure is also shown. The adoption of EBG structure in power deliver network is recommended to reduce the high frequency noise coupling between neighboring devices. These structures further help in better EMI/EMC compliance of the product by attenuating the propagation of high frequency noise between devices. The EBG structure usage can be on board, package or at die level.

IC-Package-System Integration Design

Abstract: Miniature is massive when it comes to electronics. While there exists a continuous effort in industry to integrate more functionalities into the same area, the prohibitive scaling cost at 45nm and beyond makes it difficult to continue the trend. Towards this, More-than-Moore techniques have been proposed, which explore new dimensionality of integration by creating and integrating non-digital functionality to semiconductor products (Zhang and Roosmalen. More than Moore—creating hnanoelectronics systems/nanoelectronics systems. Springer, New York, 2009). They motivate new technological possibilities and unlimited application potential.

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization

Abstract: Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel and accurate methodology is presented which can be used for any high speed Power delivery Network.

EMI and PI analysis of analog board

Abstract: The analysis object of this paper is a four-layer analog PCB board First, EMI analysis was done by simulating the radiation of this board with the hyperlynx software Thus the biggest radiation net and the longest net could be selected Near field radiation, far field radiation and S parameters analysis then would be performed to these two nets in SIwave And in Cadence software, power integrity simulation is done By setting the target impedance, this paper compares the performance of the power supply board with the target performance curve An improved method is put forward after each analysis

Power/ground wiring for high speed driver: Evaluating method by comparison with actual and simulation schemes

Abstract: In our previous studies [1], [2], good power supply wirings on a chip have provided excellent high-speed switching and tinny power swing fluctuation. In this study, we again confirmed this by higher precision re-measurements correlated with simulations. If the power integrity (PI) would be better on the circuit, the circuit would be expected that the CMOS driver makes it sure to take higher-speed switching. Such kind of scheme had not been tried previously, because the power line performance expression by SPICE tool had to be difficult to coincident with actual power line. We planed to build the power supply circuit model by SPICE tool reflected faithfully with the test coupon. As the simulation model from the transmission line for the power line is coincided with actual physical structure, we can make the concept how to design and produce circuits from the variation of simulation results. Then we can get the key design rule for over Gbps region on a input/output (I/O) interface circuit system.

Characterization and modeling of electrical stresses on digital integrated circuits power integrity and conducted emission

Abstract: Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity and the conducted emission of digital integrated circuits, clarifying the origin of electromagnetic emission evolution and proposing a methodology to predict this evolution. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip and conducted emission measurements are combined with electric stress to characterize the influence of aging. Simulations based on ICEM modeling modified by an empirical coefficient to model the evolution of the emission induced by device aging is proposed and tested.

Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling

Abstract: Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). In this paper, a new power delivery scheme called Constant Voltage Power Transmission Line (CV-PTL) is shown to significantly reduce switching noise while also lowering power consumption. This concept has been demonstrated through theory, simulation, and measurements.

Anti-resonance peak shift due to variation of effective package inductance

Abstract: Power integrity is a serious issue in the in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, peak frequency shift in the total PDN impedance in three test chips with different on-die PDN properties was observed when the package inductance was changed.

Providing non-volatile memory for suspend-to-random access memory

Abstract: A mechanism for providing non-volatile memory for suspend-to-RAM in a computer system. A method includes searching for a checkpoint message in a memory upon receipt of notification of restoring of power in a system. The checkpoint message is a confirmation of storing of state of a storage device prior to loss of the power in the system. The method also includes determining whether the checkpoint message indicates that the system reached the power integrity checkpoint. The power integrity checkpoint is a confirmation of the storing of the state of other device prior to the loss of the power in the system. The other device is different from the storage device. The method further includes restoring operating conditions of the system when it is determined that the system has reached the power integrity checkpoint.

Suppression of power-bus resonance by lossy resonator filter consisting of open stub and magnetic thin film

Abstract: Power-bus resonance of printed circuit board causes propagation of electromagnetic noise and detraction of power integrity. For suppressing the power-bus resonance at higher frequencies, we proposed a lossy resonator filter consisting of an open stub covered with magnetic thin film. First, this paper introduces the concepts of the proposed filter, especially focusing on the impedance characteristics. Then, the suppression of power-bus resonances by the proposed filter is demonstrated through full-wave simulation. As a result, it was found that the magnetic thin film formed on the open stub is promising for applying a little loss to the proposed filter. Also, full-wave simulation with an AC equivalent model demonstrated that the proposed filter achieved the desired suppression at higher frequencies over 1 GHz.

Three-dimensional packaging structure for 3D-NoC

Abstract: In this paper, we propose a novel three-dimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.

An iterative reweighting process for macromodel extraction of power distribution networks

Abstract: This paper introduces a new algorithm for the generation of optimal time-domain macromodels of power distribution networks, starting from a set of tabulated scattering responses and given a nominal termination scheme for active blocks, decoupling capacitors, and voltage regulator module. The new concept being introduced is a modified metric to characterize and optimize the accuracy of the macromodel, which takes into account the operation conditions that will be applied to run transient simulations for power integrity assessment. This metric is applied through an iterative frequency-dependent reweighting scheme in a fully automated flow. Two examples illustrate the performance of the proposed algorithm.

DC-compliant small-signal macromodels of non-linear circuit blocks

Abstract: This paper presents a novel strategy to improve the accuracy of macromodel-based approaches for fast Signal Integrity assessment for highly integrated Radio Frequency (RF) and Analog-Mixed-Signal (AMS) Systems on Chip (SoC). Specifically, we focus on small-signal representations of non-linear circuit blocks (CB) at prescribed DC operation points, which are approximated with low-order linearized macromodels to speed up the complex transient simulations required by common Signal-Integrity (SI) and Power Integrity (PI) verifications. In this paper, we propose a simple yet effective DC point correction strategy of the low-order macromodels, which enables their safe use in complete verification testbenches by ensuring exact biasing conditions for all circuit blocks. The numerical results show the effectiveness of the proposed model enhancement methodology, both in terms of accuracy and simulation time, when applied to several test cases of practical relevance for AMS and RF simulations.