Showing papers on "Power integrity published in 2015"

A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures

Abstract: Electromigration (EM) has become a major power grid reliability problem in VLSI. In this paper, we first demonstrate that EM reliability analysis of a power grid can be converted to analyzing EM reliability of the grid vias. We develop a model for calculating EM lifetime of via-arrays and observe that making power grid EM-immortal carries a huge metal area overhead and possibly makes routing of both power and signal networks too difficult to complete. We propose a method for trading off power grid integrity and reliability to minimize the total metal area overhead needed to achieve the desired grid life time under power integrity constraints. Experimental results show that using our method, both EM reliability and power integrity can be met, while the additional metal area used is significantly reduced.

Broadband Green's Function with Low Wavenumber Extraction for Arbitrary Shaped Waveguide and Applications to Modeling of Vias in Finite Power/Ground Plane

Abstract: In this paper we developed the method of broadband Green's function with low wavenumber extraction (BBGFL) for arbitrary shaped waveguide. The case of Neumann boundary condition is treated. The BBGFL has the advantage that when using it to solve boundary value problems in a waveguide, the boundary conditions have been satisfied already. The broadband Green's function is expressed in modal expansion of modes that are frequency independent. To accelerate the convergence of the Green's function, a low wavenumber extraction is performed. The singularity of the Green's function is also extracted by such low wavenumber extraction. Numerical results show that BBGLF and direct MoM are in good agreement. We next illustrate the application of BBGFL for broadband simulations of vias in printed circuit boards (PCB) by combining with the method of Foldy-Lax multiple scattering equation. The results show that BBGFL are in good agreement with MoM and HFSS. It is also shown that BBGFL is many times faster than direct MoM and HFSS. The computational efficiency in broadband simulations makes this technique useful for fast computer-aided design (CAD). The effects of waveguide or cavity structures are critical for the electrical performance of electronic devices and components in signal integrity (SI), power integrity (PI), electromagnetic interference (EMI), and electromagnetic compatibility (EMC). Harmful electromagnetic signal noises or interferences are often generated and amplified at the resonant frequencies of the waveguide or cavity structures. The issues deteriorate when the electronic devices or computer systems operate at higher frequency or faster speed. In printed circuited boards (PCBs), two adjacent power/ground planes form a waveguide/cavity structure. The propagating modes satisfy the PMC (Neumann boundary conditions) at the edges of PCB power/ground plane structures. The power/ground plane structures are the key root causes in SI/PI and EMI/EMC problems. Vias are used for vertical interconnects for multilayer PCBs. At frequencies near the resonant frequencies, the propagating electromagnetic waves excite resonant modes, that result in strong edge radiations. These cause EMI/EMC problems. The switching noises induced by voltage regulator module (VRM) generate voltage fluctuations and lead to PI problems. The high frequency power noise can also couple into signal vias and cause SI/PI coupling issues. Therefore, the modeling of PCB cavity with vias is critical in practical designs and applications of high speed PCBs and packages. Fast and accurate modeling technique is desired for broadband simulations in electronic design and application. The finiteness of the parallel power/ground planes make them waveguide/cavity structures. The power/ground planes are also of arbitrary shape. Commercial tools such as HFSS provide solutions for the analysis of the via-cavity coupling problem. The tools require large CPU and memory and are not suited for broadband analysis. The physical problem is that of TM modes in a cavity with PMC boundary conditions on the side walls. Various methods have been used for waveguide

Power and Signal Integrity co-simulation via compressed macromodels of high-speed transceivers

Abstract: This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Abstract: 3D DRAM is the next-generation memory system targeting high bandwidth, low power, and small form factor. This paper presents a cross-domain CAD/architectural platform that addresses DC power noise issues in 3D DRAM targeting stacked DDR3, Wide I/O, and hybrid memory cube technologies. Our design and analysis include both individual DRAM dies and a host logic die that communicates with them in the same stack. Moreover, our comprehensive solutions encompass all major factors in design, packaging, and architecture domains, including power delivery network wire sizing, redistribution layer routing, distributed, and dedicated TSV placement, die bonding style, backside wire bonding, and read policy optimization. We conduct regression analysis and optimization to obtain high quality solutions under noise, cost, and performance tradeoff. Compared with industry standard baseline designs and policies, our methods achieve up to 68.2% IR-drop reduction and 30.6% performance enhancement.

Active Si interposer for 3D IC integrations

Abstract: 3D IC is becoming the most promising solution for the future low power, high bandwidth, and small size semiconductor systems including computer, mobile, and network systems. In the 3D IC, Si interposer can effectively serve as the high density and high bandwidth interconnections between the chips on the interposers. Si interposer for HBM (High-bandwidth Memory Module) is an example. In this paper, we propose a new novel interposer structure which is called as “Active interposer.” In the proposed active interposer scheme, passive devices and active circuits are integrated together to enhance the signal integrity, and power integrity, and to lower power consumptions. The actives circuits in the Si interposer include equalizer, clock distribution network as well as DC-DC converter circuit. Also, wireless power delivery network can be added to reduce the number and space of P/G balls and vias.

Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

Abstract: Power integrity has become increasingly important for the designs in 32 nm or below. This paper discusses a silicon-validated methodology for power delivery (PD) modeling and simulation. Many prior works have focused on PD analysis and optimization. However, none of them provided a comprehensive modeling methodology with postsilicon data to validate the use of the models. In this paper, we present PD system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32-nm industrial double date-rate I/O design. Our models are able to capture the unique impacts of on-die inductance, state-dependent coupling capacitance, and die-package interaction. Those impacts are prominent for the designs in 32 nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for PD analysis.

Pin Assignment Optimization for Large-Scale High-Pin-Count BGA Packages Using Genetic Algorithm

Abstract: In this paper, a power/ground (P/G) pin optimization method using genetic algorithm (GA) is proposed for large-scale high-pin-count ball grid array (BGA) packages. Two objective functions are derived for signal integrity and power integrity, respectively. A general optimization flow is presented, where the basic concepts of GA optimization are introduced and some important considerations for package design are demonstrated. A customized GA flow and two accelerating strategies are developed to improve the efficiency of the optimization procedure. Using GA optimization, the P/G pin assignment of a 40 × 40 BGA package with blocks of core, inputs/outputs and differential pairs can be generated in a few tens of minutes automatically.

Efficient Analysis of Power/Ground Planes Loaded With Dielectric Rods and Decoupling Capacitors by Extended Generalized Multiple Scattering Method

Abstract: Generalized multiple scattering (GMS) method, previously proposed for signal integrity analysis of vias, is now extended to power integrity analysis of power/ground planes loaded with circular dielectric rods and decoupling capacitors. The transition matrices of the rods and decoupling capacitors are derived from boundary value problems and equivalent circuits, respectively. The transition matrices are then regarded as loads to the radial scattering matrix obtained by the GMS method. Therefore, a parallel-plate impedance matrix, which characterizes the power integrity performance, can be obtained. To understand physically different noise suppression mechanisms in power/ground planes with dielectric rods or photonic crystals, the field distributions in power/ground planes are derived in more detail. It is found that there are three kinds of resonances: one due to the cavity formed by the plane pair, one due to the cavity formed by surrounding dielectric rods, and one caused by the individual dielectric rod itself. The accuracy and efficiency of the extended GMS method are verified by comparing with a commercial full-wave solver.

Application of a New Power Distribution Scheme for Complex Printed Circuit Boards for High-Speed Signaling

Abstract: This paper presents a new power distribution scheme using power transmission lines (PTLs) applied to complex printed circuit boards. The structure consists of three daughter cards stacked on a motherboard where the board–board connectors used for connection are highly inductive. We show that in spite of the inductive connections, good signal integrity (SI) and power integrity (PI) are possible without relying too much on decoupling capacitors. This is achieved using a combination of PTL that replaces the voltage planes and current steering techniques. The PTL scheme described in this paper can be used for high-speed digital signaling. The SI and PI are demonstrated for up to 3-Gbit/s transmission between the boards.

Recent advances in electromagnetic compatibility of 3D-ICs &2013; Part I

Abstract: Electromagnetic interference (EMI) issues are becoming crucial for three-dimensional integrated components which combine multi-core Systems-On-Chip, multi-band radio frequency circuits (RF), Giga-bit memories, as well as advanced analog circuits. In this first paper, the technology roadmap towards 3D-ICs is illustrated and the associated EMC challenges are described. This first paper also focuses on the role of interposers, associated electrical parasitics, and addresses concerns about signal and power integrity.

Challenges of flip chip packaging with embedded fine line and multi-layer coreless substrate

Abstract: As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. Coreless substrate with fine-trace embedded technology is a key to achieve package miniaturization. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layers to interconnect the chip and the PCB board. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate.

Power integrity analysis for high performance design

Abstract: Power Integrity and its influence on system performance have become very important in deep sub-micrometer technology design. A robust power distribution network (PDN) is required to provide power within specified tolerance to ensure reliable operation of circuits in a system. Modeling a good PDN and performing power integrity analysis is very essential with low voltage, high transient current, high speed and high density designs. In this paper, we have discussed AC and DC analysis methodology to achieve better Power Integrity (PI). This analysis methodology provides emphasis on pre-route PI analysis. The pre-route PI analysis includes estimation of plane dimension, plane resistance/inductance, via resistance, via dimension, appropriate layer for routing, target impedance, decoupling capacitor requirements and capacitor mounting inductance. The parameters of PDN elements derived analytically are modeled as an equivalent circuit in SPICE to analyze the PDN response. The post route PI analysis performed using PI simulation matches closely with the results obtained during pre-route analysis. This analysis has been validated using actual measurement in the system in terms of DC voltage drop, ripple and transient response.

Fan-out technologies for WiFi SiP module packaging and electrical performance simulation

Abstract: The purpose of this paper is to study the Wi-Fi SiP (System-in-Package) module manufactured by the Fan-out technology, which includes dual layer RDL. In this Fan-out package, numerous components (including active chip and RLC passive components) are encapsulated by compression molding, and signals are interconnected by RDL. Without substrate (replaced by molding compound), this Fan-out package can be thinner and lower cost. Electrical simulation for RF signal integrity is also studied in this paper, to understand the Fan-out technology's characterization on RF SiP design application. To evaluate the Fan-out technology on module level performance, simulation on RF impedance matching, power integrity and thermal distribution with complete Wi-Fi SiP module is also discussed in this paper.

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating

Abstract: In traditional decoupling capacitor topologies, power gating can significantly degrade the system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance associated with the power-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: 1) relatively low-resistance through silicon vias (TSVs) and 2) ability of TSVs to bypass plane-level power networks when delivering the power supply voltage. In the proposed topologies, decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, achieving up to 50% and 87% reduction in, respectively, rms power supply and power gating (in-rush current) noise at the expense of a moderate increase in physical area and peak power consumption.

Analysis, Design, and Prototyping of Temperature Resilient Clock Distribution Networks for 3-D ICs

Abstract: The 3-D integrated circuits (3-D ICs) overcome the bottlenecks in system performance and circuit density. However, their increased power and thermal density cause temperature gradients in the chip that significantly affect signal and power integrity. Temperature gradients significantly degrade the clock signal, a key signal in digital systems, which in turn degrades system performance. In this paper, we investigate the effect of thermal gradients on the clock distribution network in the 3-D ICs along with the power distribution network. We also present power-efficient compensation methods for minimizing temperature-induced skew using the thermoelectrical analysis and use them to design a custom IC in which we compare the skew, the power, and the area. Finally, using measurements, we validate the design with a field-programmable gate array-based test vehicle.

Power integrity simulation of power delivery network system

Abstract: As a result of the increasing operating frequency and the number of transistors of IC, not only the signal integrity (SI), but the power integrity (PI) has also grown from non-existent to an important system. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE®. The accuracy of the simulation results are also compared with the measurement results.

Empirical modelling of FDSOI CMOS inverter for signal/power integrity simulation

Abstract: This paper presents a multiport empirical model based on artificial neural network for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about the I/O interface's nonlinear dynamic behavior are recorded from large signal simulation setup. The model's functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port.

Power integrity simulation of power delivery network system

Abstract: As a result of the increasing operating frequency and the number of transistors of IC, not only the signal integrity (SI), but the power integrity (PI) has also grown from non-existent to an important system. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE®. The accuracy of the simulation results are also compared with the measurement results.

Stochastic approach for Power Integrity, Signal Integrity, EMC and EMI analysis of moving objects

Abstract: In this paper stochastic approach for Power Integrity, Signal Integrity, EMC and EMI analysis of moving objects is proposed. Circuit building blocks including mixers and distributed sensors for harmonic radars are presented. Dedicated wireless links for energy transfer, designed using Bond-Wire loops with scalable geometric profile and length, are experimentally characterized. Perspectives for multi-Physics Co-Design & Co-Analysis of moving probes for efficiently coupling signal information and material properties are drawn.

Suppression of Cavity Resonant Edge Effects and PDN impedance using absorbing material

Abstract: Cavity Resonant Edge Effects (CREE) in printed circuit boards (PCBs) and packages can cause severe power integrity (PI) and electromagnetic interference/compatibility (EMI/EMC) issues. Electromagnetic radiation from PCB edges are major sources of EMI/EMC problems in electronic devices. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and packages using power vias. CREE produces considerable level of noise along the edges of PCB and package power planes due to signal coupling between vias and reflection along PCB edges with transient currents. In this paper, we investigate an approach to minimize cavity resonant noise by placing absorbing material along the edges of a PCB board. The upper peak (anti-resonant) impedance of the power distribution network (PDN) is reduced significantly. In this paper the simulated example shows the absorbing material reduces the upper impedance peaks as much as to 8% comparing to the impedance peaks without absorption material. Conclusively, the results show that adding absorbing material along the PCB edges significantly improves the noise issues by suppressing CREE.

Enhancing system-wide power integrity in 3D ICs with power gating

Abstract: Power gating is a commonly used method to reduce subthreshold leakage current in nanoscale technologies. In through silicon via (TSV) based three-dimensional (3D) integrated circuits (ICs), power gating can significantly degrade system-wide power integrity since the decoupling capacitance associated with the power gated block/plane becomes ineffective for neighboring active planes, as demonstrated in this paper. A reconfig-urable decoupling capacitor topology is investigated to alleviate this issue by exploiting the ability of via-last TSVs to bypass plane-level power networks when delivering the supply voltage. Reconfigurable decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, thereby significantly reducing both RMS power supply noise (by up to 46%) and RMS power gating (in-rush current) noise (by up to 85%) at the expense of a slight increase in area (by 1.55%) and peak power consumption (by 1.36%).

New integrated workflow for EMI simulation

Abstract: The purpose of this study is to predict electromagnetic interference (EMI) using circuit simulation integration with 2.5-D and 3-D full-wave, electromagnetic (EM) field solvers. These simulations predict the electronic system performance using signal integrity (SI), power integrity (PI) and far field radiation metrics while incorporating the entire system virtually. SPICE, IBIS, PCB layout, Connectors, and 3-D enclosures are all included within the virtual system to accurately predict system performance. The study presented in this paper shows how to simulate EMI in a complex high-speed I/O system in the time- and frequency-domains using the virtual 3-D enclosure by dynamically linking ANSYS SIwave, a specialized design platform for SI, PI and EMI analysis of electronic packages and PCBs including circuit analysis and ANSYS HFSS, a full-wave EM tool. The concepts shown in this paper can be applied to any kind of high-speed I/O system.

Reduction of PDN induced coupling into signal lines using PTL power distribution

Abstract: Transmission lines carrying high speed I/O signals can couple significant amount of electromagnetic energy to power distribution network (PDN) which can then adversely affect signal and power integrity of the entire electrical system. Similarly the reverse is also true. In this paper we present three printed circuit board designs with different power distribution topologies and show through measurement that a previously proposed PDN design based on Power Transmission Line (PTL) concept is less susceptible to coupling from signal lines.

Accurate CPM based early design stage SERDES PDN optimization in mobile platform

Abstract: As the demand of faster data rate and power domain sharing for smaller design area increases, power integrity (PI) gets more vulnerable to self and transfer noises. So it is crucial to analyze the overall PDN requirement for reliable system before fabrication. However, the traditional approach using transistor-level analysis could not be applied for a comprehensive analysis due to limited analysis turn-around time. This paper addresses a novel methodology of power delivery network (PDN) co-optimization from chip to board in early design stage to make sure the PDN quality. Accurate CPM (chip power model) is introduced to overcome the simulation time limitation. Novel design optimization method is proposed to get optimal design parameters under the given constraints. Using the proposed methodology, overall PDN design optimization process has been demonstrated with practical examples. In this case study, package design is enhanced by up to ∼ 30% inductance improvement and the number of board decoupling capacitors ∼ 80% reduction after design optimization.

Optimum configuration of SI/PI Co-Simulation using electro-magnetic simulator

Abstract: Signal Integrity (SI) of single-ended digital communication devices, like DDR memory, is directly vulnerable to Power Integrity (PI) issues because the current return path flows from power to ground through the signal lines. Accurate simulation of the interaction between both signal lines and the Power Delivery Network (PDN) is essential for estimating system reliability before fabricating the printed circuit board (PCB). To achieve this goal, electro-magnetic (EM) simulation is commonly used rather than measurement by a vector network analyzer. This simulation approach is possible, but modeling the full PDN with critical signal lines on a large PCB can absorb prohibitive long simulation time given the ever faster design cycles of modern electronics. This paper provides the pros and cons of optimizing the PDN size relative to the signal lines to reduce SI/PI Co-Simulation time for EM solvers. The results of the simulations is validated by measurement and the ideas are extended to more realistic case with deductive approach.

A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization

Abstract: Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early stage when the design database is not complete, including extraction, modeling, and optimization. This article tackles these fundamental issues of early-stage power grid design from architecture to layout. The proposed methods have been silicon validated on 32nm on-market chips and successfully applied to a 22nm design for its early-stage power grid design. The findings from such practices reveal that, for sub-32nm chips, an intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and needs to be well addressed at early stage.

A Study of Differential Signaling: Stable and Accurate Mixed-Mode Conversion and Extraction of Differential S-Parameters

Abstract: Low voltage differential signaling (LVDS) in high-speed digital systems is utilized to effectively reduce EMI and improve signal quality. Mixed-mode S-parameters are a more general way to characterize a differential network. Therefore, an accurate extraction of mixed-mode S-parameters from single-ended S- parameters is critical for Signal and Power Integrity co-simulation where SSN is generated mainly by high-frequency interconnects. The standard conversion between mixed-mode and single-ended S-parameters involves inversion of a transformation matrix. If there is no coupling, this transformation matrix is orthogonal and numerical inversion can be done accurately. In the presence of coupling, the transformation matrix depends on S-parameters and may become ill-conditioned, i.e. has high condition number, for some values of physical parameters resulting in unstable inversion of the transformation matrix and leading to highly inaccurate converted mixed-mode S-parameters. To analyze the possibility of ill-conditioning, we consider two cases: broadside coupled striplines and coupled microstrip pairs. We find that in both cases when two transmission lines are strongly coupled, the condition number becomes very large. In this case, regularized methods from the theory of ill-posed problems should be used, for example, the truncated SVD method, to obtain accurate mixed-mode S- parameters.

Test board, test system including the same, and manufacturing method thereof

Abstract: Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.

Non-orthogonal 2.5D PEEC for power integrity analysis

Abstract: Power distribution network (PDN) of a multilayered PCB is designed to supply low noise and stable power to ICs. Reduced voltage levels, increased current requirements make it challenging to attain the desired PDN impedance profile. It is therefore necessary to have multiple design iterations for optimal performance of the PDN. 3D full-wave electromagnetic solvers like the Partial Element Equivalent Circuit (PEEC) method are time constrained and therefore ill-suited for early stage design. On the other hand, 2.5D tools have lower time and memory requirements and are reasonably accurate for planar power-ground structures. For example, Multilayered Finite Difference Method (MFDM) is a 2.5D formulation suitable for PDN analysis. However, present MFDM techniques are based on orthogonal meshes, such that power-ground planes with irregular shapes and holes require unnecessarily fine mesh at the boundary for a suitable staircase approximation. In this paper, a non-orthogonal 2.5D PEEC formulation is proposed to alleviate this problem. Numerical results using quadrilateral meshes demonstrate good accuracy as compared to 3D full-wave formulation for planar geometries.

Designs of power distribution network for octa-core mobile application processor

Abstract: The high core count processor becomes the current trend to indicate the mobile devices' power. Mobile devices powered by octa-core CPUs offer faster performance, but suffer the larger dynamic voltage droops, especially for the PCB with the single-sided component placement (SSCP). Some chip-package-board co-simulations using the chip power model and full channel S-parameters were taken to evaluate the different decoupling capacitor configurations, feedback line designs, and the voltage compensation technique between the power management integrated circuit (PMIC) and the application processor (AP). Evaluation results indicated that the proposed single-ended feedback line sensed the most accurate voltage droop on the AP side than the traditional differential feedback lines did. A careful power distribution network design with the early voltage compensation technique reduced 37% of decoupling capacitor cost in the SSCP PCB and achieved the dynamic voltage droop on the AP side less than 10% of supply voltage from the PMIC.