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Showing papers on "Power integrity published in 2016"


Journal ArticleDOI
TL;DR: The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations.
Abstract: This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.

94 citations


Proceedings ArticleDOI
01 May 2016
TL;DR: Fan-out WLP interconnection and BGA substrate design with fine pitch Cu pillar bumps was presented in this article, where the authors considered signal integrity (SI) and power integrity (PI) to achieve high speed and high bandwidth data center application.
Abstract: A novel multi-chips Fan-out Wafer Level Package (FOWLP) with fine pitch Cu pillar bumps was presented to accommodate volumes of I/O requirements on a BGA organic substrate. Due to the manufacturing limitation, cost and reliability consideration of fine-pitch BGA substrate, chips with extremely fine pitch RDL routing (width/space=2/2um) and a 2.nD wafer level carrier was integrated as system-in-package (SiP) to resolve I/O capacity issue. Besides, multi-chips with small die size connected through wafer-level RDL was also developed to resolve low yield issue of large chip in advanced wafer process. In this paper, a comprehensive design methodology was introduced to cover fan-out WLP interconnection and BGA substrate design. A test vehicle built in TSMC N16 process was presented to verify the design methodology. With fully consideration on signal integrity (SI) and power integrity (PI), hundreds of interconnection I/Os with 4Gbps speed were achieved. Besides, high speed SERDES with 25Gbit/sec data rate was also verified to enable high speed and high bandwidth data center application.

50 citations


Journal ArticleDOI
TL;DR: In this article, a methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented.
Abstract: A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

31 citations


Journal ArticleDOI
TL;DR: This paper reviews the basics of black-box macromodeling and illustrates several application scenarios that are relevant for the EMC community, including Signal and Power Integrity, lossy transmission line modeling, electromagnetic full-wave simulation, network equivalencing and transformer modeling.
Abstract: The main idea of black-box macromodeling is to approximate the dynamic behavior of complex systems in terms of lowcomplexity models or equivalent circuits. Such compact models can be derived through robust numerical algorithms, such as the Vector Fitting scheme, starting from frequency- or time-domain responses of the system, and without any specific knowledge of its internal structure. The excellent accuracy that can be achieved, combined with the reduced size of the models, has led to a widespread adoption of this approach in several electrical and electronic applications, allowing designers to perform numerical simulations at the system level with high efficiency. This paper reviews the basics of black-box macromodeling and illustrates several application scenarios that are relevant for the EMC community, including Signal and Power Integrity, lossy transmission line modeling, electromagnetic full-wave simulation, network equivalencing and transformer modeling.

28 citations


Proceedings ArticleDOI
25 Jul 2016
TL;DR: In this paper, the root-omega method applied to the cases with smooth and rough conductors is validated using simulations, and potential errors in the procedure are discussed, as well as the potential errors of the procedure.
Abstract: Accurate frequency-dependent dielectric properties are important for accurate modeling of signal and power integrity problems. One method for extracting dielectric properties from fabricated multilayer printed circuit boards is based on the measured electrical property of fabricated transmission lines, denoted the “Root-omega” method. In this paper, the “Root-omega” method applied to the cases with smooth and rough conductors is validated using simulations. Potential errors in the procedure are discussed.

17 citations


Proceedings ArticleDOI
08 May 2016
TL;DR: Power-aware signal integrity (PI-SI) analysis of data group signals of an onboard DDR4 memory module using power-aware IBIS model is presented and simultaneously switching noise (SSN) response of data bus and crosstalk between nearby channels is simulated.
Abstract: Designing data channels for the DDR4 memory is a challenging due to high data rates of 3.2GB/s per data signal at a low-voltage of 1.2V The coupling of simultaneous switching noise (SSN) in data signals in DDR4 memory modules is a critical signal and power integrity (SI/PI) problem. It is important to catch SI and PI problems at an early stage in design that requires fast and accurate power-aware signal integrity analysis. In this paper, power-aware signal integrity (PI-SI) analysis of data group signals of an onboard DDR4 memory module using power-aware IBIS model is presented. DDR4 power plane and data signals are analyzed using 3D Electromagnetic based PI-SI solver then the transient simulation is performed on combined PI data of power plane and data signals to get simultaneously switching noise (SSN) response of data bus and crosstalk between nearby channels.

16 citations


Journal ArticleDOI
TL;DR: A new multiport power-aware behavioral model formulation and extraction for high-speed input/output buffers that enable the transient prediction of power and ground bouncing effects under simultaneously switching output (SSO) buffers for signal and power integrity evaluation is presented.
Abstract: This paper presents a new multiport power-aware behavioral model formulation and extraction for high-speed input/output (I/O) buffers that enable the transient prediction of power and ground bouncing effects under simultaneously switching output (SSO) buffers for signal and power integrity evaluation. The derivation of the proposed model is based on the analysis and extension of the I/O buffer information specification (IBIS) buffer issue resolution documents (BIRDs) (i.e., BIRD-95.6 and BIRD-98.3) and the macromodeling via parametric identification of logic gates (Mpilog) (i.e., artificial neural network). The analysis of the previous IBIS and Mpilog modeling approaches is followed by a new model formulation that integrates both the previous BIRDs with a well-designed characterization and parametric extraction procedure. The accuracy and computational performances of the proposed model is evaluated under a realistic SSO scenario.

13 citations


Patent
29 Feb 2016
TL;DR: In this paper, a broadband Green's function computation technique that employs low-wavenumber extraction on a modal summation is used to model the waveguide behavior of electronic components, systems, and interconnects on a printed circuit board.
Abstract: A broadband Green's function computation technique that employs low wavenumber extraction on a modal summation is used to model the waveguide behavior of electronic components, systems, and interconnects on a printed circuit board. Use of the broadband technique permits discretizing the surface of the printed circuit board across a wide range of frequencies all at once. The broadband Green's function is also extended to via waveguides on circuit boards and power/ground plane waveguides of arbitrary shape. Such a method can analyze a given circuit board geometry over a broad frequency range several hundred times faster than is otherwise possible with existing commercial analysis tools. The present method is useful in electronic design automation for analyzing signal integrity and power integrity, reducing electromagnetic interference and ensuring electromagnetic compatibility.

12 citations


Journal ArticleDOI
Shaowu Huang1, Xiaoning Ye1, Nan Kang1, Beomtaek Lee1, Kai Xiao1 
TL;DR: In this article, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances in high-speed interconnects and a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor.
Abstract: In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

12 citations


Journal ArticleDOI
TL;DR: An overview of the state-of-the-art in I/O-buffer behavioral modeling is presented, introducing the main features of both standard and emerging solutions.
Abstract: Modern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for systemlevel simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the stateof- the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed.

11 citations


Proceedings ArticleDOI
Kyungjun Cho1, Hyunsuk Lee1, Joungho Kim1
01 Jan 2016
TL;DR: The designed HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module shows good signal integrity and electrical performance of the HBMinterposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain.
Abstract: Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

Proceedings ArticleDOI
08 May 2016
TL;DR: This paper presents a novel iterative method for finding an equivalent set of poles and residues of a system from its discrete frequency domain response, and has extensive applications in the modeling and simulation of signal and power integrity structures.
Abstract: Frequency-domain modeling and simulation of systems is performed widely today; however, time-domain transient simulation of systems often requires synthesis of network S/Y/Z-Parameters as lumped equivalent circuits. In turn, circuit synthesis requires determination of the set of poles and residues implied by the network parameters. This paper presents a novel iterative method for finding an equivalent set of poles and residues of a system from its discrete frequency domain response. Each iteration chooses up to 3 consecutive samples from the given response to find a local fit; such iterations are repeated until the sum of all local fits matches the given response within a specified target error, across the entire designated bandwidth. The proposed method is demonstrated for two test cases: 1) microstrip and 2) power planes. PRESS has extensive applications in the modeling and simulation of signal and power integrity structures; such as, high-speed signal and power delivery interconnect networks of electronic packages and printed circuit boards.

Proceedings ArticleDOI
01 Sep 2016
TL;DR: A novel iterative method that approximates a multi-port frequency responses to an equivalent circuit netlist consisting of the basic elements - resistor, capacitor and inductor, demonstrating the potential of the method for signal/power integrity modeling and simulation of interconnect networks.
Abstract: Interconnects in electrical/electronic systems are commonly modeled in frequency-domain. However system level electrical analysis involving signal and power integrity simulations are typically done in time-domain, which calls for circuit level representation of the interconnect networks. In this paper, we demonstrate a novel iterative method that approximates a multi-port frequency responses to an equivalent circuit netlist consisting of the basic elements — resistor, capacitor and inductor. Each iteration picks a few consecutive points from the frequency response, identifies a local transfer function matching their response and synthesizes it as a branch in the approximant. A 3-port network comprised of power delivery planes with three vias is synthesized. The equivalent circuit response closely matches the given frequency response, demonstrating the potential of the method for signal/power integrity modeling and simulation of interconnect networks.

Journal ArticleDOI
TL;DR: In this paper, an efficient numerical method for evaluating the radiation emission from power-bus structure in complex electronic packaging of high-speed integrated circuit system is presented based on the discretization technique and the boundary integral equation.
Abstract: The ground bounce noises in a power distribution network of multilayered stack-ups in electronic packages and boards will cause simultaneous switching noise coupling, high insertion loss degradation of signal via, and stray radiation. These lead to signal integrity, power integrity, and electromagnetic compatibility problems. This paper presents an efficient numerical method for evaluating the radiation emission from power-bus structure in complex electronic packaging of high-speed integrated circuit system. It is based on the discretization technique and the boundary integral equation. First, the variational field distribution on the peripheral surfaces of power-bus structure induced by the return current is calculated by using the Helmmholtz equation and boundary conditions. The peripheries of power–ground (P/G) planes and via are discretized into small elements. Then, the changing transient impedance at the edge of antipad plate caused by displacement current through P/G planes is calculated with the assumptive exciting current 1 mA. Finally, the far field radiation is obtained through equivalent magnetic current of edge field. Cavity-model analysis is used to verify, and the good agreement with the theoretical prediction validates the correctness and efficiency of the present analysis.

Proceedings ArticleDOI
05 Jun 2016
TL;DR: A run-time simulation framework of both PD and architecture and captures their interactions that has the capability to simulate benchmarks with millions of cycles within reasonable time and illustrates multiple over-pessimisms in traditional methodologies.
Abstract: With the reduced noise margin brought by relentless technology scaling, power integrity assurance has become more challenging than ever. On the other hand, traditional design methodologies typically focus on a single design layer without much cross-layer interaction, potentially introducing unnecessary guard-band and wasting significant design resources. Both issues imperatively call for a cross-layer framework for the co-exploration of power delivery (PD) and system architecture, especially at early design stage with larger design freedom. Unfortunately, such a framework does not exist yet in the literature. As a step forward, this paper provides a run-time simulation framework of both PD and architecture and captures their interactions. Enabled by the proposed recursive run-time PD model, it handles an entire PD system on-the-fly simulation with <1% deviation from SPICE. Moreover, with a seamless interaction among architecture, power and PD simulators, it has the capability to simulate benchmarks with millions of cycles within reasonable time. A support vector regression (SVR) model is employed to further speed up power estimation of functional units to millions cycle/second with good accuracy. The experimental results of running PARSEC suite have illustrated the framework's capability to explore hardware configurations to discover the co-effect of PD and architecture for early stage optimization. Moreover, it also illustrates multiple over-pessimisms in traditional methodologies.

Journal ArticleDOI
TL;DR: The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators.
Abstract: This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulations.

Journal ArticleDOI
TL;DR: In this article, the authors present a methodology for on-chip power-noise modeling in the early stage of system-on-chip (SoC) design, which enables modeling of the dynamic current profile, without any geometry information and estimation of SoC power noise in the register-transfer-level design phase.
Abstract: This paper presents a novel methodology for on-chip power-noise modeling in the early stage of system-on-chip (SoC) design. Conventionally, the on-chip power-noise simulation is performed in “placement and routing” design stage. Therefore, designers experience difficulty in applying the simulation results to improve power-noise performance because of the delivery time. The proposed methodology enables modeling of the dynamic current profile, without any geometry information and estimation of SoC power noise in the register-transfer-level design phase. Each SoC sub-block is defined as a unit simplified chip power model (SCPM), and the defined unit SCPMs are integrated into one SCPM, including multiblock characteristics. SCPM presents various types of current profiles to accurately predict the maximum current peak, and it includes the background current to prevent overestimation of the ac current. To improve the simulation accuracy, this paper proposes a voltage ripple measurement method that considers the SoC operating scenario. The simulation results of the SCPM are verified by the measurement results, and the SCPM methodology shows the correlation results of 7 and 18 mV on two test vehicles with a 1.1 V core voltage. In the chip-package design industry for electronic applications, the proposed methodology presents a design guide for the power delivery network, such as essential capacitance per location (e.g., chip, package, and printed circuit board) and the limit of the off-chip routing inductance. In addition, the forecast by the SCPM simulation shows that preactive design is available at the early stages of the design process.

Proceedings ArticleDOI
01 Aug 2016
TL;DR: In this paper, the authors used the method of test and simulation to study the near-end and far-end crosstalk between signal lines in high-speed circuit transmission line.
Abstract: With the rapid development of high density packaging technology, signal integrity of packages has become a hot research field. The signal integrity related problems, including noises (Delay, Reflection, Crosstalk between different line, etc.), bus timing design and power integrity issues, may seriously affect the performance of whole electronic system and even cause this system fail to work. This article is based on basic theory of the signal integrity at high - speed circuit transmission line, use the method of test and simulation to study the near-end crosstalk and far-end crosstalk among signal lines. Test and analysis the crosstalk at large scale integrated circuit package CQFP240M. Build micro-strip line and strip-line model through simulation software, to simulate and test the influence factors of crosstalk between adjacent transmission lines. And put forward crosstalk reduction method and optimized design rule according to the simulation results.

Proceedings ArticleDOI
25 Jul 2016
TL;DR: This work simulated and analyzed the mobile Application Processor (AP) GPU system based on Chip Power Model (CPM) and applied GPU's current model to simulate simultaneous switching noise and power noise in the chip PDN.
Abstract: These days, mobile devices require low-power consumption. To meet these requirements, IC's operating voltage is continuously lowered. As a result, power noise margin decreases which require more precise Power Distribution Network (PDN) design. In this work, we simulated and analyzed the mobile Application Processor (AP) GPU system based on Chip Power Model (CPM). We applied GPU's current model to simulate simultaneous switching noise and power noise in the chip PDN. To verify the model and simulation set-up, we measured voltage ripple and compared with simulation. We concluded that our simulation setup is reliable and conducted power integrity case studies for the future PDN design.

Patent
21 Sep 2016
TL;DR: In this article, a power distribution network design method based on a decoupling region of decoupled capacitors is proposed. But the problem of the installation position of the decouplings capacitor cannot be solved, and a rapid, simple and convenient method is provided for selection and placement of the capacitor in the power distribution networks.
Abstract: The invention discloses a power distribution network design method based on a decoupling region of a decoupling capacitor. The power distribution network design method comprises the steps of: firstly, based on a resonant cavity model, modeling a power ground plane with decoupling capacitors; based on the modeling method, calculating out transverse and longitudinal decoupling radii of the decoupling capacitors; according to a frequency point corresponding to the maximum amplitude of an impedance of an input output port, selecting the required decoupling capacitor, and according to the transverse and longitudinal decoupling radii of the decoupling capacitor, selecting an installation position of the decoupling capacitor; and finally, drawing an impedance curve of a power distribution network. According to the invention, the problem that in the power distribution network design, the installation position of the decoupling capacitor cannot be obtained is solved; a rapid, simple and convenient method is provided for selection and placement of the decoupling capacitor in the power distribution network, and reliable guidance is provided for power integrity design in the practical engineering.


Dissertation
01 Jan 2016
TL;DR: In this article, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow to guarantee the power integrity on an industrial design.
Abstract: Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC and increase in the operating frequencies has immensely changed the classical understanding of noise in the new age complex ICs. Switching noise specifically has become a dominating criteria for high performance digital and mixed signal ICs. Voltage variations on the power/ground nodes of a circuit is a type of switching noise affecting digital and mixed-signal ICs. Therefore, power integrity (PI) has become a critical challenge that must be addressed at the system level considering the parasitic effects of package and board. In this work, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow. This methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This approach has been successfully exploited to guarantee the power integrity on an industrial design. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins.

Proceedings ArticleDOI
Yeon-Chang Hahm1, Ming Li1, John Yan1, Yuri Tretiakov1, Hai Lan1, Scott Chen, Simon Wang 
18 Aug 2016
TL;DR: In this article, the authors employed embedded trace substrate (ETS) with careful signal designs and deployments of power planes to reduce power noise and designing dense traces become a challenging part of the design processes.
Abstract: Advanced memory technologies such as DDR4 and LPDDR4 are able to receive and transmit huge amount of data in faster and more efficient ways than ever before. At the same time, reducing power noise and designing dense traces become a challenging part of the design processes. In particular, high signal density on a package naturally restricts the resources for robust power delivery when keeping the same package layer count. While the costly thin-core packaging technology is widely available, embedded trace substrate (ETS) packaging technology is another viable solution at a reduced price. This work employs ETS substrate with careful signal designs and deployments of power planes. Essential part of the ETS package design includes the power delivery network (PDN) design in conjunction with Power Supply Induced Jitter (PSIJ) sensitivity from the silicon circuits. At the same time, critical components of the power rail noise needs to be suppressed by on-die and on-package decoupling capacitances. After iterative designs and simulations for ETS package, about 92% of overall PDN noise and 86%~95% of jitter impact were estimated compared to thin-core package, and 88% of tJIT(per) and 93% of tJIT(cc) have been achieved in the measurements.

Proceedings ArticleDOI
21 Mar 2016
TL;DR: A method for calculating the simultaneous switching noise (SSN) in a PDN is explored, based on the approximation of the frequency domain impedance of PDN by rational functions and the vector fitting method.
Abstract: The power distribution network (PDN) is constituted by interconnection networks that connect voltage regulator module (VRM) through the printed circuit board (PCB) followed by the packaging paths until integrated circuit. The PDN of an electronic system can increase the noise due to the internal activity of the circuit. In fact, the miniaturization of the device can transmit the power supply noise to the integrated circuit and superposed with the useful signals. What affects the power and signal integrity. These phenomena reduce the operating speed and reliability of the circuit. In this paper we explore a method for calculating the simultaneous switching noise (SSN) in a PDN, based on the approximation of the frequency domain impedance of PDN by rational functions and the vector fitting method. The simulation results in this, paper are verified by MATLAB and PSPICE tools.

Proceedings ArticleDOI
17 May 2016
TL;DR: In this article, an analysis of the filtering characteristic for a coplanar symmetrical meander lines structure is presented, where the effects of geometrical parameters, which are length of vertical and horizontal elements as well as the distance of the gap between two symmetrical lines, on the filtering property of the structure are discussed.
Abstract: This paper presents an analysis of the filtering characteristic for a coplanar symmetrical meander lines structure. The effects of geometrical parameters, which are length of vertical and horizontal elements as well as the distance of the gap between two symmetrical lines, on the filtering property of the structure are discussed. A novel direct derivation of the filtering performance of the coplanar configuration based on our proposed circuit model is also addressed. The mentioned analysis could be a useful guidance in the design stage of a uniplanar filter to enhance the signal and power integrity as well as immunity of Integrated circuits

Proceedings ArticleDOI
01 Oct 2016
TL;DR: It is shown how multiscale FDTD simulations can be accelerated with model order reduction, and a passivity argument is used to systematically guarantee the stability of the resulting scheme, which is a main novelty with respect to previous works.
Abstract: The Finite-Difference Time-Domain (FDTD) method is widely used in signal and power integrity, applied electromagnetism, and physics. Unfortunately, its computational efficiency can be severely degraded for multiscale problems, where small and large features coexist. This scenario is common in signal and power integrity, because of the large aspect ratio of interconnects and power/ground planes. In this paper, we show how multiscale FDTD simulations can be accelerated with model order reduction. A detailed model for complex objects is first generated using a fine FDTD grid. The model is then compressed with model order reduction, and embedded into a main coarse grid. During this process, the stability limit of the reduced model can be also extended, enabling the use of a larger time step in the whole domain. Using a passivity argument, we are able to systematically guarantee the stability of the resulting scheme, which is a main novelty with respect to previous works. A numerical example with two reduced models shows the potential of the proposed ideas.

Journal ArticleDOI
Baekseok Ko, Joowon Kim, Jaemin Ryoo, Chulsoon Hwang1, Chan Keun Kwon, Soo-Won Kim 
TL;DR: The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs by combining vector network analyser measurements with an on-chip model for power integrity analysis and shows good agreement with the measurement results.
Abstract: The authors present a practical design process that considers the power noise problem in CPU blocks for application processors used in smart TVs. The target impedance is determined by modelling the RLC circuit of a system-on-chip power net. The target impedance of a power delivery network is then determined by applying the extracted chip current profile for finalising the design budget. The authors modelled the on-chip power net by combining vector network analyser measurements with an on-chip model for power integrity analysis. The authors demonstrated the optimisation and design strategy by using a ball grid array ball interconnection and case studies on the placement of multilayer ceramic capacitors. The simulation results showed good agreement with the measurement results. The error in the minimum value (negative direction) by voltage droop was less than 8.6%, while the difference in voltage noise ripple was 2.69% for a criterion of 1.1 V assuming a worst-case condition of 1.2 V.

Proceedings ArticleDOI
01 Aug 2016
TL;DR: In this article, a planar electromagnetic band-gap (EBG) structure is proposed to suppress simultaneous switching noise in low frequency range and expand the stop-band bandwidth, which is achieved by increasing the connection bridge between the patches.
Abstract: Simultaneous switching noise is the main reason that greatly affects power integrity of power distribution network. In order to suppress simultaneous switching noise in low frequency range and expand the stop-band bandwidth, we propose a new type planar electromagnetic band-gap (EBG) structure which is achieved by increasing the connection bridge between the patches. It can be directly embedded in high-speed circuit PCB. When the suppression depth is −30dB, the stop-band is 0.29–7.21GHz. The proposed electromagnetic band-gap structure can effectively decrease the lower cutoff frequency and expand the stop-band bandwidth which is confirmed by simulation.

Proceedings ArticleDOI
01 Oct 2016
TL;DR: Post layout power integrity simulation for Solid State Drive PCB using Mentor Graphics Hyperlynx PI simulation tool is discussed and a stable DC voltage within the specified voltage ripple limits across the frequencies of interest is provided.
Abstract: Today in high-speed digital design, system-level Power Integrity (PI) analysis has become inevitable due to ever increasing data rates for both serial I/O interface and memory interface. The present trend in high-speed digital circuits is increasing speed and density, thereby consuming more current and operating at lower supply voltages. The increase in switching speed and total current consumption combined with lower supply voltages has decreased the noise margin making the components more susceptible to power supply noise. The objective of Power integrity analysis is to provide a stable DC voltage within the specified voltage ripple limits across the frequencies of interest. In this paper post layout power integrity simulation for Solid State Drive PCB using Mentor Graphics Hyperlynx PI simulation tool is discussed.

Proceedings ArticleDOI
17 May 2016
TL;DR: In this paper, a transient simulation analysis for printed circuit board (PCB) power distribution network (PDN) by using physics-based circuit model is proposed, where PCB PDN is divided into different blocks.
Abstract: A transient simulation analysis is proposed for printed circuit board (PCB) power distribution network (PDN) by using physics based circuit model. The PCB PDN is divided into different blocks. Different modeling methods are used to provide physics-based circuit models for each block. Then, Hspice simulation is used to do transient simulation for the PCB PDN based on the circuit.