Showing papers on "Power integrity published in 2018"
01 Jul 2018
TL;DR: This article consists only of a collection of slides from the author's conference presentation.
Abstract: This article consists only of a collection of slides from the author's conference presentation.
31 citations
01 Jul 2018
TL;DR: The main novel contribution of this work is the formulation of the model fitting equations in a decoupled form, which allows for a very efficient implementation in case of interconnects with a large number of interface ports, as typically required in Signal and Power Integrity applications.
Abstract: This paper introduces an algorithm for the construction of reduced-order macromodels of electrical interconnects starting from their sampled scattering responses. The produced macromodels embed in a closed-form an approximate dependence of the model equations on external parameters such as geometrical dimensions or material characteristics. The resulting parameterized models are easily cast as parameter-dependent SPICE netlists, which can be used for system-level Signal and Power Integrity assessment via numerical simulation, including sensitivity and optimization tasks. The main novel contribution of this work is the formulation of the model fitting equations in a decoupled form, which allows for a very efficient implementation in case of interconnects with a large number of interface ports, as typically required in Signal and Power Integrity applications. The parameterized models are guaranteed stable and passive for any configuration of the external parameters, thus ensuring stable transient numerical simulations.
11 citations
01 Dec 2018
TL;DR: A comparative study between different surrogate modeling techniques as applied to PI analysis is described and a reliable and fast coarse models to make trade off decisions while complying with voltage levels and power consumption requirements are developed.
Abstract: In recent years, extensive usage of simulated power integrity (PI) models to predict the behavior of power delivery networks (PDN) on a chip has become more relevant. Predicting adequate performance against power consumption can yield to either cheap or costly design solutions. Since PI simulations including high-frequency effects are becoming more and more computationally complex and expensive, it is critical to develop reliable and fast models to understand system’s behavior to accelerate decision making during design stages. Hence, metamodeling techniques can help to overcome this challenge. In this work, a comparative study between different surrogate modeling techniques as applied to PI analysis is described. We model and analyze a PDN that includes two different power domains and a combination of remote sense resistors for communication and storage CPU applications. We aim at developing reliable and fast coarse models to make trade off decisions while complying with voltage levels and power consumption requirements.
10 citations
01 Jul 2018
TL;DR: In this paper, a physics-based circuit modeling methodology is proposed for system level power integrity (PI) analysis, which connects the footprints of geometry details to the PDN input impedance looking into the system from the IC chip.
Abstract: A physics-based circuit modeling methodology is proposed in this paper for system level power integrity (PI) analysis. The circuit model is extracted by following the current paths in the system PDN based on cavity model and plane-pair PEEC models. The modeling methodology connects the footprints of geometry details to the PDN input impedance looking into the system from the IC chip. With further reductions of the physics-based circuit model, an engineering circuit model which explains the hierarchical charge delivery mechanism is proposed. The engineering circuit model reveals the role of PDNs from each level in the system. A commercial PDN system with a complex organic package, high-layer-count printed circuit board, and IC is used to validate the modeling methodology in the paper. The PDN input impedance has a good match with the impedance profile simulated with a commercial PI analysis tool for the system. The engineering circuit model is also validated for the PI analysis. The modeling methodology illustrates the fundamental physics in the PDN charge delivery and can be used for other PI analysis later.
9 citations
TL;DR: This paper addresses an unfamiliar direct time-domain model of a 3-D multilayer hybrid PCB that is validated with a three-port network prototype constituted by the six-layer PCB, including passive SMD components.
Abstract: The multilayer technology constitutes the ultimate solution for the design of high-density printed circuit board (PCB). Challenging modeling method is required to predict the signal integrity (SI) of the multilayer PCB. This paper addresses an unfamiliar direct time-domain model of a 3-D multilayer hybrid PCB. The subnetwork primitive elements of the equivalent graph are constituted by lumped components, interconnect lines, vias, pads, and anti-pads. The tensorial analysis of networks (TANs) is used to solve the problem related to the graph topology in the function of the PCB design parameters. The TAN concept is based on the interaction between the primitive elements. The mesh currents constitute the proposed computational unknowns. The unfamiliar model is validated with a three-port network prototype constituted by the six-layer PCB, including passive SMD components. In the frequency domain, S-parameter validation from 100 kHz to 5 GHz is presented. By using 80-Mb/s and 0.5-Gb/s rate data patterns, the proposed TAN model is validated by both simulations and measurements in the time domain. The transient results present vector magnitude relative error accuracy lower than 15%. Thanks to the computation speed and adaptability to multilayer hybrid structures, the TAN model is a prominent approach for the SI and power integrity analyses of 3-D multilayer structures.
9 citations
26 Mar 2018
TL;DR: A simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double-data-rate three (DDR3) memory module is presented.
Abstract: In this paper, a simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double-data-rate three (DDR3) memory module is presented. For SI issues, the chip-package-board simulation indicates how to improve eye diagram by eliminating non-ideal effects of the most crucial part of the channel. For PI issues, the SI/PI co-simulation is concerned with the power distribution network (PDN) and the distribution of decoupling capacitors (De-Caps). In addition, the optimized set of de-caps by simulation provides a cost-effect way to meet the desired target impedance for acceptable simultaneous switching noise (SSN) generated in PDN due to I/O switching. Finally, the co-simulation methodology can indicate SI/PI problems before IC tape-out and reduce circuit design cycle as well.
7 citations
TL;DR: In this paper, a modal approach for parallel plate impedance and equivalent inductance extraction for power integrity analysis including ball grid arrays (BGAs) between two parallel plates is presented.
Abstract: A modal approach for parallel plate impedance and equivalent inductance extraction for power integrity analysis including ball grid arrays (BGAs) between two parallel plates is presented. Since the BGAs are placed close to each other, the current flowing through each ball is not uniformly distributed due to the proximity effect. In this paper, a modal-based cavity method is proposed to count for this proximity effect. Analytical solutions for both the parallel plate impedance and the equivalent inductances associated with the BGAs are derived from the modal-based cavity method. The proposed method is validated by finite element method simulations and the application of the proposed method for power distribution network design is demonstrated.
7 citations
TL;DR: A novel two-layered RDL design in low-power double data rate fourth generation (LPDDR4) application is proposed by proposing a novel power/ground meshed layout for superior PI performance.
Abstract: The emerging wafer-level packaging (WLP) technology suffers from serious signal integrity (SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious parasitic effects by the high-density RDL traces and less flexibility of decoupling capacitors, so the robust power distribution network is critical to design. This paper proposed a novel two-layered RDL design in low-power double data rate fourth generation (LPDDR4) application by proposing a novel power/ground meshed layout for superior PI performance. Besides, the second-order RLC simplified model and normalized resistance are derived to handle the process scaling issue for successful SI by adjusting the cross-sectional structure of RDL so that LPDDR4 4266 can work well on 2- $\mu \text{m}$ WLP.
7 citations
26 Mar 2018
TL;DR: Two efforts to make computational electromagnetic algorithms compatible to machine learning methods are introduced: solving method of moments (MoM) can be seen as a training training process, and the artificial neural network could be used to solve MoM naturally through training.
Abstract: While machine learning is becoming a demanding request in every corner of modern technology development, we are trying to see if we could make computational electromagnetic algorithms compatible to machine learning methods. In this paper, we introduce two efforts in line with this direction: solving method of moments (MoM) can be seen as a training training process. Consequently, the artificial neural network (ANN) could be used to solve MoM naturally through training. Amazon Web Service (AWS) can be used as the computations platform to utilize the existing hardware and software resources for machine learning. Another effort regarding to the nonlinear IO of ICs can be modeled through ANN. Hence, a behavior model with growing accuracy can be obtained for the signal integrity and power integrity analysis. It can be further hybridized into discontinuous Galerkin time domain (DGTD) method for CEM characterizations. Benchmarks are provided to demonstrate the feasibility of the proposed methods.
7 citations
01 Oct 2018
TL;DR: Several packaging configurations integrating high bandwidth and density DRAM and high performance SOC will be compared in terms of power delivery and thermal dissipation and two kinds of SIP will be analyzed.
Abstract: The advanced packaging technologies including POP (package on package), SIP (system in package), embedded substrate, WLP (wafer-level package) and FO (fan-out) package have been utilized to achieve the small form-factor, high density, and high performance SOC package for mobile hand-held device. [1, 2] As the clock frequency of computation-intensive cores including CPU, GPU, and NPU increases, the impact of power delivery and temperature control of 3D package on the upper limit of performance becomes bigger and bigger. In this paper, several packaging configurations integrating high bandwidth and density DRAM and high performance SOC will be compared in terms of power delivery and thermal dissipation. POP and two kinds of SIP will be analyzed. POP has been popular packaging structure used for smart phone application, which has given small form-factor with high bandwidth DRAM package over SOC package. Although the flexibility and scalability provided by POP has been attractive in mobile terminal, SIP is being considered to maximize the performance of SOC within limited form-factor in hand-held device. Two kinds of SIP including side-by-side SIP and stacked SIP will be determined. While side-by-side SIP configuration is constructed by stacked SOC dies and stacked DRAM dies which are placed side-by-side, stacked SIP configuration is constructed by stacked DRAM dies on SOC dies which are interconnected by TSV (through silicon via). While side-by-side SIP configuration is more attractive than other configurations in thermal-perspective with several conditions, stacked SIP configuration has more advantage in terms of power delivery. Based on the power delivery network impedance and thermal violation region graph given by thermal resistance matrix [11], the comprehensive analysis including power integrity and thermal characterization will be presented with several POP and SIP configuration.
7 citations
TL;DR: A large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation is presented.
Abstract: This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.
TL;DR: A novel approach is presented for an integrated analysis of power distribution networks, including dc–dc converters, power transmission lines (PTLs), and multiple loads, based on cascaded matrix representation of interconnects.
Abstract: In this paper, a novel approach is presented for an integrated analysis of power distribution networks, including dc–dc converters, power transmission lines (PTLs), and multiple loads. The effect of power interconnects is investigated on the dynamic characteristics of a pulsewidth-modulated buck converter. A closed-form relation is developed for control-to-output transfer function including the power interconnects as a transmission line model. The effect of PTLs is demonstrated on converter’s open-loop transfer function and its stability. For analysis of distributed power loads on printed circuit board PTLs, a model is developed based on cascaded matrix representation of interconnects. The model is successfully tested against planar electromagnetic simulation results.
01 May 2018
TL;DR: A systematic approach to design M-Link in the extreme condition is proposed and modulated chip power model (MCPM) technology is applied to ensure System-PDN and INFO SI/PI.
Abstract: MediaTek INFO Link (M-Link) is worldwide first successful homogeneous DIE-to-DIE data link for high-speed networking application. Considering benefits from large on-die capacitance of core-power domain, merged power domain for INFO and core-power is adopted. However, in order to sustain over 250W external core-power interference and internal INFO SSO noises, optimization of whole band target impedances to against these noises becomes one of major challenges. In this paper, a systematic approach to design M-Link in the extreme condition is proposed. In first part of paper, modulated chip power model (MCPM) technology is applied to ensure System-PDN. MCPM is modulated CPM which serves as new current load to represent mid-frequency bands interference for system level time domain noise simulations. In the second part, input pattern modulation (IPM) was applied to predict worst power ripple on INFO I/Os and jitter from sensitive circuit critical path. The IPM methodology serves as a total assessment considering all SI/PI impact to ensure a robust design. Finally, given fully consideration on System-PDN and INFO SI/PI, INFO I/Os with 4.8Gbps speed achieved 70% ETT eye windows in both simulation and verification. The design trade-off on core-power merged and separated is also discussed for future higher system bandwidth requirement.
01 May 2018
TL;DR: This study demonstrated capability of TFI package in view of electrical performance, cost effectiveness and process challenges by co-design modeling and process optimizations.
Abstract: TSV-Free Interposer (TFI) packaging technology was developed for central/graphics processing unit (CPU/GPU) and stacked memory system-in-package (SiP) applications. TFI package is targeting to accommodate thick module as High Bandwidth Memory (HBM) and wide-bus interconnections between CPU/GPU and HBM in a package with cost-effective process. The redistribution layer structure was studied based on inter-chip connectivity between CPU/GPU and HBM as well as signal integrity and power integrity. This study demonstrated capability of TFI package in view of electrical performance, cost effectiveness and process challenges. The process challenges were overcome by co-design modeling and process optimizations.
01 Jul 2018
TL;DR: This presentation presents a meta-analysis of the die/Package/Board co-design methodology for power integrity analysis and discusses the importance of impedance measurement in the design of power supplies.
Abstract: •Industry trend and power integrity challenges •Capacitor •Power impedance measurement •Power decoupling strategy •Target impedance •On-die power integrity analysis •Package-level power integrity analysis •Die/Package/Board co-design methodology •SSO and SSI •Open topics and Q&A
22 May 2018
TL;DR: How the package behavior can change depending on the interaction with PCB parameters is shown, and a methodology to optimize on-package decoupling taking into account the system variability is proposed.
Abstract: A key aspect of power integrity in modern electronic systems is the choice and optimization of decoupling capacitors. Traditionally, this issue has been addressed at PCB level, but the integration of discrete SMD capacitors inside BGA package substrates is becoming more and more common in complex high-speed digital devices. In the context of semiconductors industry, the on-package decoupling applied to digital microcontrollers needs to be defined, often without any clear information on system configuration. This paper shows how the package behavior can change depending on the interaction with PCB parameters, and proposes a methodology to optimize on-package decoupling taking into account the system variability.
01 Nov 2018
TL;DR: The purpose of this paper is to analyze the various design challenges in High Speed embedded systems, related to Signal Integrity (SI) and Power Integrity (PI) and the practical solutions to overcome these challenges.
Abstract: The demand for smaller size, lesser weight, lower power, higher performance and faster speed has set the trend for multi-threaded and multi-core CPU based embedded design. Such design are associated with various challenges which includes space constraints, trace routing constraints, length matching, signal integrity, power integrity, EMI/EMC constraints and thermal management. Systematic design approach and simulations helps to address these challenges in the design stage itself thereby reducing the time to market. The purpose of this paper is to analyze the various design challenges in High Speed embedded systems, related to Signal Integrity (SI) and Power Integrity (PI) and the practical solutions to overcome these challenges.
01 Mar 2018
TL;DR: In this paper, a proper truncation scheme is proposed to handle the situation where the outer boundary is PEC or PMC, and its effectiveness is demonstrated by numerical cases in numerical cases.
Abstract: The analytical formula of the via barrel-plate capacitance has been widely used for the analyses of signal integrity, power integrity and electromagnetic compatibility of via-plate-pair structures by way of a physics-based via circuit model. This formula involves an infinite summation which must be truncated in real calculation. An improper truncation could result in underestimated or even unphysical values. This paper extends our previous study to handle the situation where the outer boundary is PEC or PMC. A proper truncation scheme is proposed to address the above truncation issues. Its effectiveness is demonstrated by numerical cases.
01 Jul 2018
TL;DR: In this article, power density spectra were used to determine random signals once measurement techniques for the near field have been employed to capture stochastic signals, and the Poynting vector was calculated and post processing algorithms applied to determine the stochastically signals' physical location and power density value.
Abstract: The presented methodology allows for the analysis of stochastic signals using an automated near-field measurement system and real-time signal analyzer. In the method below, power density spectra were used to determine random signals once measurement techniques for the near field have been employed to capture stochastic signals. Traditional methods for measurement within the near field identify either the electric (E) or magnetic (H) distributions and, depending on the processing capability of the analyzer used, a description of the time variant signal. It has been observed during the analysis of the measured complex signals that neither the H nor E field distributions have a direct relation to the stochastic field location; as such, a mathematical formula has to be applied to calculate the power density value and position. In the provided method, it is essential that both E and H fields be independently measured in the near field so that the complete complex signal be acquired. Once both fields have been quantified over the same time period and superposition is resolved, the true phase angle can be determined. From the resulting data a Poynting vector can be calculated and post processing algorithms applied to determine the stochastic signals' physical location and power density value. This technique can, through a backscatter analysis, determine if any signal returns to the source, so as to assess if there are any impacts on Signal Integrity or Power Integrity.
22 May 2018
TL;DR: Differences in design specifications between automotive and mobile SoC package designs are examined and the implications to Power Integrity are examined.
Abstract: The demand for connected smart cars has grown exponentially in the past few years. To meet consumer's digital lifestyle needs and take part in this emerging market, microprocessor companies, such as Intel®, are shifting a focus to automotive SoC package designs. This paper examines the differences in design specifications between automotive and mobile and the implications to Power Integrity. The automotive use case, temperature cycling, and reliability qualifications are more stringent and add to the Power Integrity challenges. Frequency and time domain simulations were performed for all Fully Integrated Voltage Regulator (FIVR) and non-FIVR rails and compared between automotive vs. mobile.
01 Dec 2018
TL;DR: In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed.
Abstract: In this paper, the imperativeness of low power distribution network (PDN) impedance on printed circuit board (PCB) with high frequency signals operating at hundreds of Mega-Hz range and the impact of embedded capacitance material (ECM) in minimizing wideband PDN impedance are discussed. The study to compare the performance of PCB with ECM versus conventional dielectric FR4 material was conducted with post-layout power integrity simulation using Keysight ADS on the power net of interest, followed by measurement of PDN impedance and simultaneous switching noise (SSN) using network analyzer (VNA) and oscilloscope respectively on prototype PCB. Lastly, eye diagram and jitter of the high frequency clock signal on the PCB are observed. The correlated simulation and measurement results are presented and discussed in the later section of this paper.
01 Oct 2018
TL;DR: In this paper, the authors present an advanced packaging solution that provides ultra-high density interconnects between dies by embedding a passive bridge die in the organic substrate, and outline the signal and power integrity simulation flows for this new packaging solution along with corresponding validation data.
Abstract: Embedded Multi-die Interconnect Bridge (EMIB) is an advanced packaging solution that provides ultra-high density interconnects between dies by embedding a passive bridge die in the organic substrate. This paper outlines the signal and power integrity simulation flows for this new packaging solution along with the corresponding validation data.
01 Jul 2018
TL;DR: A novel type of EBG structures is proposed to suppress the noise on the printed circuit board (PCB) and achieves the effect of ultra-wideband high isolation and meets the power and signal integrity requirements of high-speed mixed-signal backplane based on VPX(VITA 46).
Abstract: In this paper, the problem of simultaneous switching noise (SSN) in the design of high-speed mixed-signal backplane is analyzed from the aspect of power integrity. How to suppress SSN of high-speed mixed-signal backplane becomes an important research direction at present. Based on the analysis of the traditional decoupling capacitor noise reduction method and the latest noise reduction principle of the electromagnetic band gap (EBG) structures, a novel type of EBG structures is proposed to suppress the noise on the printed circuit board (PCB). The simulation and measurement results show that the noise isolation depth reaches −40dB in the frequency band from 0.4 to 20GHz, which achieves the effect of ultra-wideband high isolation and meets the power and signal integrity requirements of high-speed mixed-signal backplane based on VPX(VITA 46). It provides an experimental reference for the application of the EBG structure on other high-speed mixed-signal backplane and other projects.
01 May 2018
TL;DR: Through virtual prototyping, in depth analysis and comparing the effectiveness of the display module with and without proper signal & power integrity design considerations is made possible.
Abstract: With increasing market demand for the automotive instrumental clusters to be more interactive and scalable, the trend is now moving towards a full digital display system. Thus, there is more electromagnetic compatibility (EMC) design focus on the display module. In EMC design, it would be inadequate if signal & power integrity designs are not taken into considerations. In this paper, the use of 3D full wave modeling is applied on an automotive display module. Through virtual prototyping, in depth analysis and comparing the effectiveness of the display module with and without proper signal & power integrity design considerations is made possible.
01 Dec 2018
TL;DR: In this article, active silicon interposer (ATSI) was developed to reduce system cost as well as provide wide bandwidth, and the power integrity of the ATSI was analyzed.
Abstract: Active silicon interposer (ATSI) was developed to reduce system cost as well as provide wide bandwidth. ATSI package is targeting to accommodate large FPGA with wide I/O. The power integrity of the ATSI is analyzed. The power distribution network (PDN) in the package includes metallic mesh network, TSV and ball grid array (BGA). The line width and the gap of the mesh network are chosen as 75 μm and 25 μm. Small slots are added in the metal line in order to meet the metal density requirement. Six TSVs are designed to connect the metallic mesh network to one BGA through the backside RDL. MIM capacitors are specially embedded under the top metallic layer near the chip micro bump to reduce the PDN impedance. A portion of the PDN with size of 2.4×2.4 mm2 is modelled and simulated to estimate the performance of the whole PDN structure.
01 Dec 2018
TL;DR: A high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements.
Abstract: An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements.
01 Nov 2018
TL;DR: Through the proposed methodology, the supply noise induced jitter is reduced 800% at the output eye-diagram of 28 Gbps high speed serial link, compared with the design without PDNs enhancement, and also without package manufacturing cost increment.
Abstract: This paper presents an IC package co-design methodology to reduce power supply noise induced jitter for 28 Gbps high speed serial link in tsmc 28nm technology with 10-layers FCBGA substrate. To reduce the supply noise induced jitter, the package design is enhanced at the power distributed networks (PDNs) in layout design phase. The enhancements are reduction at power supply parasitic inductance and isolation at cross-power domains. Through the proposed methodology, the supply noise induced jitter is reduced 800% at the output eye-diagram of 28 Gbps high speed serial link, compared with the design without PDNs enhancement, and also without package manufacturing cost increment.
TL;DR: Today's mobile and interconnected society poses complex and growing challenges to the electronic systems that back emerging big data and Internet of Things technologies, and ensuring their signal and power integrity (SPI) is essential to safeguarding their functionality and interoperability.
01 May 2018
TL;DR: The most effective parameters for the design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration, which can be achieved as low as 35 mW on this rate.
Abstract: For over 20 GHz board level I/O interface circuits, the most serious problem is its high power consumption due to arrange adequate signal forming (pre-emphasis, adaptive equalizer, etc.) and timing adjust circuits that generally require 200 mW/lane for 28-56 Gbps interface. To reduce the power consumption, binary signal (Non Return to the Zero, NRZ) transmission system is fitted to eliminate easily above arrangements. Implementation with FR-4 printed circuit board (PCB) would be an only solution to tackle the problem of production cost of the transmission system. It is well known there are many technical challenges to realize over 200 mm transmission line for signal integrity even with 10 Gbps. With our simulation based analyses, we found that many studies have discussed signal integrity (SI) and power integrity (PI) issues only the range from MHz to 10 GHz of frequency. So it is necessary to consider the transmission parameters of the entire frequency range from direct current (DC) for high-speed I/O circuits especially in transistor level, because MOS devices need constant voltage for the switching operation. In this study, total I/O interface circuit, from CMOS driver through package interconnection to CMOS receiver, is examined mainly by simulation basis for 28 to 56 Gbps signaling. Three types of design were chosen as high speed differential driver / receiver device models, and the transmission characteristics were compared for the SI. One model is developed with TSMC's 65 nm IP, and other models are with 32 nm and 20 nm fin structure models of the Arizona State University's Predictive Technology Model (PTM). The PI parameters for the 40 mm and 200 mm wiring on PCBs, package with capacitors, and chip wiring including on-chip capacitor were studied to reach as possible as ideal voltage source by S-parameter simulation from DC to 100 GHz. We achieved the successful results of the target performance of 56 Gbps in some considered configuration. And the power consumption of our design can be achieved as low as 35 mW on this rate. The most significant aspect to realize our circuit design is the co-design among all I/O circuit parameters. The most effective parameters for our design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration. We made the configuration of the PDF (PDN) at resonance frequency as high as 6.5 GHz. The driver device models examined in this study exhibited no explicit differences in performance up to 56 Gbps.