Showing papers on "Power integrity published in 2019"

System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration

Abstract: A brand new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoIC^™), has been successfully developed to integrate active and passive chips into a new integrated SoC system to meet ever-increasing market demands on higher computing efficiency, wilder data bandwidth, higher functionality packaging density, lower communication latency, and lower energy consumption per bit data. 3D packaging is challenging and requires overcoming three major challenges - thermal, power delivery, and yield. The SoIC, as industry-first 3D logic-on-logic and memory-on-logic chiplet stacking technology platform, enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies, all to be integrated in a single, compact new system chip. From external appearance, SoIC looks like a general SoC chip with multiple pre-designed heterogeneous functional chips embedded. As SoIC is fabricated using "front-end" process, it can be holistically integrated into variant "back-end" advanced packaging technology platforms such as flip chip, integrated fan-out (aka InFO), 3DIC, and 2.5D with Si interposer (e.g. CoWoS^™) [1-2] to provide a miniaturized and highly integrated HI SiP for the future HPC, AI, 5G, and edge computing applications. With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 μm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions. In this paper, we demonstrated for the first time an integration of SoIC chip into InFO_PoP without increasing its form-factor. The SoIC was made on a logic-on-logic stacking to validate the design rules, process maturity, and reliability.

From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration

Abstract: With the reduced noise margin brought by relentless technology scaling, power integrity assurance has become more challenging than ever. On the other hand, traditional design methodologies typically focus on a single design layer without much cross-layer interaction, potentially introducing unnecessary guard-band and wasting significant design resources. Both issues imperatively call for a cross-layer framework for the co-exploration of power delivery (PD) and system architecture, especially in the early design stage with larger design and optimization freedom. Unfortunately, such a framework does not exist yet in the literature. As a step forward, this paper provides a run-time simulation framework of both PD and architecture and captures their interactions. Enabled by the proposed recursive run-time PD model, it can achieve smaller than 1% deviation from SPICE for an entire PD system simulation. Moreover, with seamless interactions among architecture, power and PD simulators, it can simulate actual benchmarks within reasonable time. The experimental results of running PARSEC suite have demonstrated the framework’s capability to discover the co-effect of PD and architecture for early stage design optimization. Moreover, it also shows multiple over-pessimism in traditional PD methodologies. Finally, the framework is able to investigate the impact of dynamic noise on system level oxide breakdown reliability and shows 31%–92% lifetime estimation deviations from typical static analysis.

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Abstract: A new trend in complex SoC design is chiplet-based IP reuse using 2.5D integration. In this paper we present a highly-integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5D designs. We chipletize each IP by adding logical protocol translators and physical interface modules. These chiplets are placed/routed on a silicon interposer next. Our package models are then used to calculate PPA and signal/power integrity of the overall system. Our design space exploration study using our tool flow shows that 2.5D integration incurs 2.1x PPA overhead compared with 2D SoC counterpart.

Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity

Abstract: With the development of internet and the rise of artificial intelligence industry, the high performance semiconductor integrated circuits have become a hot product in the semiconductor industry. The 2.5D IC package with ultra-high density I/O is the first structure applied on high performance computing (HPC) like GPU. Applied on GPU or HPC, there is an ASIC die and multiple HBM dice on silicon interposer. Between ASIC die and HBM die, there are lots of high speed signal lines between them and over hundreds of thousands of small vias. But the productivity of silicon interposer is always issue to realize the ultra-high density I/O products. To consider the productivity and performance, TSV-less structure like FOCoS (Fan-Out Chip on Substrate) is proposed by few years ago. There are Chip First FOCoS and Chip Last FOCoS for different process and application. In this paper, a real case with an ASIC die and 2 HBM dice is designed in 2.5D IC and Chip Last FOCoS structures. In this real case, the interposer design and Fan-Out RDL is utilized SiP-id (System in Package intelligent design) design platform to accelerate the ultra-high density I/O routings. In addition, the electrical performance including signal integrity (SI) and power integrity (PI) are compared between 2.5D IC and Chip Last FOCoS. From the analysis results, the dynamic power noise between the two structures is showed in this paper and the electrical performance of HBM2 and 28Gbps SerDes I/Os are displayed as well.

Multi-Objective Optimization of Decoupling Capacitors for Placement and Component Value

Abstract: A multiobjective evolutionary method is proposed for the optimization of surface mount device (SMD) multilayer ceramic chip (MLCC) capacitors used for decoupling on printed circuit boards (PCBs) with resonant power–ground plane pairs. The proposed approach provides options for designers to meet power integrity specifications by employing uniform-valued capacitors that help to reduce the bill-of-material (BOM) cost and mitigate the part procurement risk. It is also shown that uniform MLCC capacitors with variable distance from power pins can have a similar decoupling effect to an assortment of capacitors. By simultaneously optimizing the pin-capacitor distance and value, the proposed method is shown to allow for the allocation of fewer decoupling capacitors under the ball-grid-array (BGA) pin field of an integrated circuit (IC) device.

A Novel System-Level Power Integrity Transient Analysis Methodology using Simplified CPM Model, Physics-based Equivalent Circuit PDN Model and Small Signal VRM Model

Abstract: The goal of a well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise and errors delivered to chip. This paper provides power integrity engineers a guideline to model PDN agilely in a simplified method and choose specific voltage regulator module model under specific circumstances. These comparisons and studies present the advantage of this novel methodology using equivalent circuit model for system level power integrity transient analysis.

A Novel Framework for Parametric Loewner Matrix Interpolation

Abstract: The generation of black-box macromodels of passive components at the chip, package, and board levels has become an important step of the electronic design automation (EDA) workflow. The vector fitting (VF) scheme is a very popular method for the extraction of such macromodels, and several multivariate extensions are now available for embedding external parameters in the model structure, thus enabling model-based variability analysis and design optimization. The Loewner matrix interpolation framework was recently suggested as an effective and promising alternative macromodeling approach to VF. In this article, we propose a parametric version of Loewner interpolation, which embeds orthogonal polynomials as an integral part of the parameterization framework. This approach is shown to be efficient and accurate and presents various advantages with respect to competing multivariate rational interpolation methods. These advantages include better control of model smoothness in the parameter space and a particularly efficient implementation of the singular value decomposition, which is the core of the model extraction scheme. These advantages are confirmed through several examples relevant for signal and power integrity applications.

Power Noise and Near-Field EMI of High-Current System-in-Package With VR Top and Bottom Placements

Abstract: Integrated voltage regulators (IVRs) support an increasing number of voltage domains while enhancing the transient response and enabling fine-grained dynamic voltage frequency scaling. A voltage regulator (VR)-on-package is a promising IVR topology, which supports high-voltage transmission within a printed circuit board and package, leading to lower distribution loss. A power delivery network within a VR-on-package environment is presented in this paper. This paper also presents a study of VR top- and bottom-placement topologies within a system-in-package environment in terms of electromagnetic interference (EMI) and power integrity. This comparative analysis targets a specific server package application, and the power integrity evaluation is focused on the power delivery network between the VR and IC. The VR top-placement topology exhibits more than $3\times $ less EMI and 15.3% lower worse case IR drop as compared with the VR bottom-placement topology. The tradeoffs are, however, a greater package power loss and higher package cost due to the larger number of package layers in the VR top-placement topology. The VR top-placement topology exhibits a 52.6% higher power loss through the package than the VR bottom-placement topology.

A New SI-PI co-Simulation Approach for Efficient Consideration of Coupling Between PDN and SDN

Abstract: As the clock frequency of SOC (system on a chip) including core circuits like CPU and GPU and various IOs like LPDDR4, LPDDR5, and SERDES, increases, the impact of SDN (signal delivery network) and PDN (power delivery network) on the functional stability and low power operation of corresponding circuit blocks becomes more and more important. However, there has been the challenge to the design and verification with co-simulation of SI (signal integrity) and PI (power integrity) considering the coupling between SDN and PDN due to a painful long simulation time, which is usually not allowed in the short design cycles required by modern electronics especially in mobile hand-held devices. This paper will provide a matrix formulation for SI-PI co-simulation in frequency-domain to reduce the simulation time and consider the coupling efficiently.

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Abstract: This work is based on the vision that the ultimate power integrity and efficiency may be best achieved via a heterogeneous chain of voltage processing starting from onboard switching voltage regulators (VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs. As such, we propose a heterogeneous voltage regulation (HVR) architecture encompassing regulators with complimentary characteristics in response time, size, and efficiency. By exploring the rich heterogeneity and tunability in HVR, we develop systematic workload-aware power management policies to adapt heterogeneous VRs with respect to workload change at multiple temporal scales to significantly improve system power efficiency while providing a guarantee for power integrity. The proposed techniques are further supported by hardware-accelerated machine learning (ML) prediction of nonuniform spatial workload distributions for more accurate HVR adaptation at fine time granularity. Our evaluations based on the PARSEC benchmark suite show that the proposed adaptive three-stage HVR reduces the total system energy dissipation by up to 23.9% and 15.7% on average compared with the conventional static two-stage voltage regulation using off-chip and on-chip switching VRs. Compared with the three-stage static HVR, our runtime control reduces system energy by up to 17.9% and 12.2% on average. Furthermore, the proposed ML prediction offers up to 4.1% reduction of system energy.

High Density IO Fan-out Design Optimization with Signal Integrity

Abstract: With the development of the Internet and the rise of artificial intelligence industry, high - performance semiconductor integrated circuits have become a popular product in the semiconductor industry. The 2.5D IC package with ultra-high density I/O is the first structure to be used in high performance computing (HPC) such as GPUs. The silicon interposer applied to GPU or HPC has an ASIC chip and multiple HBM chips. However, the productivity of silicon interposer is always a problem for the realization of ultra - high density I/O products. For considering productivity and performance, TSV-less structure such as FOCoS (fan-out chip on the substrate) was proposed by a few years ago [1]-[5]. There are different processes and applications for Chip First FOCoS and Chip Last FOCoS. In this paper, a real situation with ASIC chip and 2 HBM chips is designed using the 2.5D IC and Chip Last FOCoS structure. In this reality, the interposer and the Fan-Out RDL design are used to accelerate ultra-high density I/O routing by using the SiP-id design platform. Electrical performance including signal integrity (SI) and power integrity (PI) was compared between 2.5D ICs and Chip Last FOCoS. From simulation results, this paper shows transient power supply noise between the two structures and shows the electrical properties of HBM2 and 28Gbps SerDes I/O.

Hybrid Approach for Large Size FC-BGA to Enhance Thermal and Electrical Performance Including Power Delivery

Abstract: A new approach to flip chip package with hybrid packaging technologies is presented, which will be pretty much promising package solution as a large size FC-BGA (flip chip ball grid array) for SOC (system on a chip). The proposed new approach can be utilized to enhance power integrity and heat spreading and to reduce the FC-BGA package height with keeping and not degrading the mechanical property of conventional FC-BGA. The presented new package based on hybrid approach is implemented by the combination of thick-core based substrate and thin-core (or coreless) substrate. While most of area in package is mechanically supported by 800um thick core, SOC die is mounted on thin substrate by proper flip chip bonding. The interconnection between thick-core based substrate and thin-core (or coreless) substrate is achieved by wire bonding by conventional packaging process or RDL (redistribution layer) by fan-out package technology. Comparative study on the proposed new structure with conventional FCBGA is presented in terms of power integrity, signal integrity, and thermal resistance. Through several case studies, it is demonstrated that the presented hybrid approach is an adequate package solution for cost-effective thin FCBGA enhancing power integrity and thermal performance.

Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm

Abstract: Decoupling capacitors are fundamental keys for the reduction of transient noise in power delivery networks; their arrangement and values are crucial for reaching this goal. This work deals with the optimization of the decoupling capacitors of a power delivery network by using a nature-inspired algorithm. In particular, the capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function. An experimental board is designed and manufactured; measurements are performed to validate the numerical results.

Design and Analysis of MIM Capacitor on Power Integrity Effects for HPC and Network Applications

Abstract: In this work, we investigate power integrity (PI) effects of using metal-insulator-metal (MIM) capacitors for high power applications. As transistor density for integrated circuitry increases at advanced process nodes, the PI management of high power applications becomes more challenging. MIM capacitor offers a possible solution to overcome these issues by acting as a fast response charge tank. The MIM capacitor mentioned here was designed for high-power IP with about $2 mW/$um2 at 1GHz. Based on the simulation results, PI properties was analyzed by the designed MIM capacitor considering offchip parameters. As a result, it is demonstrated that the worst and the average of dynamic voltage drop (DVD) are improved by 22.5% and 42.5%, respectively when compared to the case without MIM capacitors. In addition, usage of MIM capacitors reduces the package decap requirement by 54% to meet same target voltage drop. Consequently, the usage of MIM capacitor is advantageous to make high power IP blocks stable in an integrated chip. Thus, it is expected to develop the design methodology of effective MIM usage and investigate system-level optimal capacitor configuration considering various decoupling capacitors such as on-die capacitor, MIM capacitor, and package decoupling capacitor.

Open Defect Detection of Through Silicon Vias for Structural Power Integrity Test of 3D-ICs

Abstract: Increasing test coverage of power integrity in manufacturing test of 3D-ICs is necessary to achieve zero DPPM (Defect Parts Per Million) in the market. Although only functional tests are applied to analog circuits such as power distribution networks in general, applying structural tests will increase the coverage. This paper proposes to measure resistance between a pair of bumps under TSVs (Through Silicon Vias) to detect open defects of the TSVs as a part of structural power integrity test. Diagnostic performance of each bump pair is evaluated by simulations and the best one is selected to detect each TSV defect. Resistance threshold for the defect detection is determined considering trade-off between fault coverage and yield loss. Experimental simulations of power distribution network in a 3DIC with 2 dies are conducted and the trade-off between them is derived.

Closed-Form Multipole Debye Model for Time-Domain Modeling of Lossy Dielectrics

Abstract: Lossy dielectrics in printed circuit boards and integrated circuit packages can be represented by using a Debye model. This allows accurate signal and power integrity analysis, which depends on the accuracy of material properties of the board or package. Such a Debye model needs multiple poles for accurate representation of the loss tangent over a broad frequency range. Electromagnetic and circuit simulations can then include the impact of frequency-dependent dielectric constant and loss. In this letter, we present an efficient and closed-form multipole Debye model, automating the modeling of lossy dielectrics for inclusion in time-domain electromagnetic or circuit simulators.

Analysis of Power Supply And Signal Integrity of High Speed PCB Board

Abstract: High-speed circuit boards are an inevitable trend in the development of electronic systems at this stage. Signal integrity and power integrity issues caused by high-speed and high-density environments cannot be ignored. This paper studies the high-speed integrated PCB signal integrity and power integrity. First, the basic concepts of high speed, high density, signal integrity and power integrity are clarified. The research status of signal integrity and power integrity at home and abroad is introduced. Finally, the basic causes and influencing factors and feasible solutions are studied.

Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

Abstract: To reduce the noise created by a power delivery network, the number, the value of decoupling capacitors and their arrangement on the board are critical to reaching this goal. This work deals with specific improvements, implemented on a genetic algorithm, which used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values. Measurements are performed on a specifically manufactured board in order to validate the effectiveness of the proposed algorithm and the optimization results obtained for a specific example board.

Power Delivery Network Optimization Approach using an Innovative Hybrid Target Impedance

Abstract: A well-designed power delivery network (PDN) demands a set of efficient and effective modeling and optimization methodology for the Chip-Package-PCB System. This paper work provided and validated the hybrid target impedance for the PDN impedance optimization in frequency domain and the physics-based equivalent circuit model with small signal model for voltage response validation in time domain. The hybrid target impedance defined with current profile-based discrete and continuous target impedance. Two key impedance points in discrete were identified for on-chip worst case switching scenario and voltage regulator module switching ripple, more points can be added if specific core power switching scenario identified. The continuous impedance points are from the conventional target impedance by voltage ripple to dynamic current change. This hybrid method provides a more effective and convergent way to perform system level decoupling capacitors optimization in frequency domain and to meet voltage specification in time domain, also to avoid overdesigning for cost saving.

PI/SI Analysis and Design Approach for HPC Platform Applications

Abstract: In this work, we introduce a comprehensive methodology for the power integrity/signal integrity analysis of SoC and silicon-based interposers in a HPC platform. By conducting a comprehensive investigation of the global chip-level PDN impact by electrical interactions between the chip, package, and board in the system, an efficient power delivery network was designed to meet HPC specifications. This was achieved by extracting long-term test scenarios (microsecond-order duration) to estimate voltage drop at the bumps and deployment of decoupling capacitors considering the optimal placement and numbers within an allowable cost budget. This analysis also yielded the benefit of reduction in power domains/ball count/package layers which further reduced costs. In addition to the Power Integrity, signal properties were analyzed under the allowed channel conditions (channel width and spacing, shielding lane placement). As a result, the channel design parameters are found to meet the criteria of eye opening including power noise and crosstalk effects. It was demonstrated that the electrical properties of the HBM2e IP are successfully operational up to 3.2Gbps.

Improved Structure for Package Substrates with Embedded Thin-Film Capacitor

Abstract: Embedding thin-film capacitors (TFC) in a package substrate is a technology aimed at improving the performance of power supply. The package substrate that we have developed and produced embeds TFCs into the core layer of a built-up substrate. Using this substrate promises to dramatically reduce the impedance on power supply lines and provide a stable power supply to the integrated circuit (IC) chip, resulting in improved performance of electronic devices. In this paper, we propose three improved structures for package substrates with embedded TFCs: the first is an asymmetric single-sided embedded TFC structure that uses the warpage-control layer; the second is a standalone embedded TFC structure that places solitary TFCs directly under the IC chip only; the third is a coreless embedded TFC structure that embeds TFCs in a coreless substrate. These technologies promise to help lower the cost of package substrates, increase their efficiency, and reduce their thickness.

Direct Simulation of the Full-Wave Partial Element Equivalent Circuit Using Standard SPICE [Application Notes]

Abstract: The partial element equivalent circuit (PEEC) [1] is a computational electromagnetic (EM) method featuring circuit-oriented solutions for full-wave (FW) EM problems. An arbitrary threedimensional structure consisting of conductors and dielectric/magnetic materials can, after proper discretization, be transformed into an equivalent circuit composed of inductors, capacitors, and controlled sources that may be solved using a Simulation Program With Integrated Circuit Emphasis (SPICE)-like simulator or can be combined with external lumped circuits in a straightforward manner. Classical and recent applications of PEEC include interconnect modeling [2], [3], power integrity analysis [4], transient lightning modeling [5], transient electrostatic discharge simulation [6], power electronics [7], antenna analysis [8], [9], and modeling of magnetic materials [10]. Three very good and in-depth treatments of the subject can be found in [11]–[13].

A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures

Abstract: The segmentation method used for the analysis of arbitrarily shaped planar structures is extended to a more general form to account for capacitive loading between parallel plates. In power integrity (PI) analysis of power delivery networks (PDN), the capacitive loading represents decoupling capacitors between power and ground planes. The algorithm is geared to the analysis of PDNs for performance evaluation, selection and placement of decoupling capacitors. For linear circuits, the proposed integrated algorithm eliminates the commonly used two-step approach. In the case of nonlinear loads, the algorithm helps to reduce the size of modified admittance matrix (MNA) and relaxes the burden of following circuit simulation. The proposed method is validated in comparison to a numerical electromagnetic (EM) simulator.

Electrical and Thermal Co-Analysis of Thermally Efficient SiP for High Performance Applications

Abstract: Applications including artificial intelligence, 5G mobile communication, and virtual reality require a large amount of computations, wide bandwidth, and high-speed data transmissions with very low error levels. The system-in package (SiP) becomes a promising solution to satisfy those requirements. Not only the SiP has a smaller form factor, but also it provides improved signal integrity because the shorter channel length can be achieved. The decreased distance between the logic chips and the memories lower the insertion loss, the crosstalk level, and therefore the signal degradation can be minimized. However, a high level of the system integration in the SiP and the high computing performance can result in a poor thermal management. The high computing performance requires increasing the transistor densities in various IPs, and the switching speeds of the transistors. This leads to increased power consumptions, which cause large thermal dissipations. The thermal dissipations in the package aggravate transistor performance, which yields an overall performance degradation or system malfunctions. Using heat spreader or high thermal conductive material can mitigate the thermal issues, but they are insufficient solutions. In order to improve the thermal management in the SiP, a novel SiP structure is introduced. The proposed SiP has thermal dissipation paths, which is called thermal chimney, from logic/memory dies to the heat spreader. The thermal chimney is high thermal conductive material, and it establishes a direct channel for heat flowing from the chip to the heat spreader to reduce the temperature in the package. In this study, the thermally efficient SiP geometry, how it cools down the package temperature and the manufacturing process will be described. The electrical and thermal performance will be analyzed when assuming the SiP consists of modems and DRAM memories.

Enabling fast power integrity transient analysis through parameterized small-signal macromodels

Abstract: In this paper, we present an automated strategy for extracting behavioral small-signal macromodels of biased nonlinear circuit blocks. We discuss in detail the case study of a Low DropOut (LDO) voltage regulator, which is an essential part of the power distribution network in electronic systems. We derive a compact yet accurate surrogate model of the LDO, which enables fast transient power integrity simulations, including all parasitics due to the specific layout of the LDO realization. The model is parameterized through its DC input voltage and its output current and is thus available as a SPICE netlist. Numerical experiments show that a speedup up to 700X is achieved when replacing the extracted post-layout netlist with the surrogate model, with practically no loss in accuracy.

Power Integrity Comparison of Off-chip, On-interposer, On-chip Voltage Regulators in 2.5D/3D ICs

Abstract: Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

TSV with Embedded Capacitor for ASIC-HBM Power and Signal Integrity Improvement

Abstract: This paper presents the analysis of through silicon via (TSV) with embedded capacitor for impedance tuning to improve the power integrity (PI) performance of Application-Specific Integrated Circuit – High Bandwidth Memory (ASIC-HBM) system. The crosstalk due to TSV with embedded capacitor (TSV-Cap) to signal integrity (SI) performance is evaluated by analyzing its frequency response up to 100 GHz and its eye diagram. Using this TSV-CAP, the power distribution network (PDN) impedance is kept below 50 mΩ up to 5 GHz while achieving data rate of 5 Gbps.

Robustness to Voltage Noise With Ring Oscillator Clocks

Abstract: Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of power delivery networks (PDNs). Lower supply voltages were made possible with technology scaling, but power density was also increased. Consequently, power integrity became a key factor in the design of reliable high performance circuits. Ring oscillators clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise. However, the effectiveness highly depends on the design parameters of the PDN, power consumption patterns, and spatial locality of the ROC within the clock domain. This paper analyzes the impact of the PDN parameters and ROC location on the voltage noise and the robustness achieved by using ROCs. The capability of reacting instantaneously to large voltage droops makes ROCs an attractive solution, which also allows to relax the constraints required for the PDN design. The experiments show that up to 83% of the margins for voltage noise and up to 27% of the total leakage power can be reduced by using ROCs. In addition, PDN simplifications are possible, with fewer power interconnections or package decoupling capacitors of lower quality. Tolerance to voltage noise and related benefits can be increased with multiple ROCs.

A Generalized Segmentation Algorithm for Planar Resonant Structures with Discrete Components

Abstract: A compact relation is developed based on the indefinite impedance matrix. The proposed technique generalizes the application of the segmentation method to arbitrarily shaped planar structures including the effect of lumped circuit components. The components are accounted for by modifying the previously used terminal relations in the development of the segmentation method. The proposed algorithm targets power integrity (PI) applications in printed circuits and integrated circuit packages. By direct computation of distributed circuit parameters of planar power delivery networks (PDN) including discrete components, the need for a second phase circuit simulation is eliminated. An application of the proposed method is demonstrated on a practical circuit and the results are validated in comparison to a numerical electromagnetic (EM) simulator.

Effect of SSN on signal and power integrity on 32-bit microcontroller : Modeling and correlation

Abstract: This paper presents a methodology to create a Simultaneous Switching Noise (SSN) predictive SPICE model for a 32-bit microcontroller. Here, the purpose is to predict the noise interference generated by switching IOs and establish new design/layout rules for the next product generation in order to reduce these interferences. This model achieves an accurate correlation between measurements done on a 32-bit MCU and Eldo simulations. Then, features are defined in order to build this accurate model. Having this, a deeper research work can be done only by simulation.