scispace - formally typeset
Search or ask a question

Showing papers on "Power integrity published in 2020"


Journal ArticleDOI
TL;DR: A deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs) that provides an optimal decap design that satisfies target impedance with a minimum area.
Abstract: In this article, we first propose a deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs). The proposed method provides an optimal decap design that satisfies target impedance with a minimum area. Using deep RL algorithms based on reward feedback mechanisms, an optimal decap design guideline can be derived. For verification, the proposed method was applied to test power distribution networks (PDNs) and self-PDN impedance was compared with full search simulation results. We successfully verified by the full search simulation that the proposed method provides one of the solution sets. Conventional approaches are based on complex analytical models from power integrity (PI) domain expertise. However, the proposed method requires only specifications of the PDN structure and decap, along with a simple reward model, achieving fast and accurate data-driven results. Computing time of the proposed method was a few minutes, significantly reduced than that of the full search simulation, which took more than a month. Furthermore, the proposed deep RL method covered up to $10^{17}$ – $10^{18}$ cases, an approximately $10^{12}$ – $10^{13}$ order increase compared to the previous RL-based methods that did not utilize deep-learning techniques.

40 citations


Journal ArticleDOI
TL;DR: In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented, and the results are validated with a place-and-route (P&R)-based physical implementation flow.
Abstract: In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

27 citations


Proceedings ArticleDOI
13 Jul 2020
TL;DR: The PISA multiprocessor chip with improved power robustness for space applications is introduced which is successfully produced and tested in IHP 130 nm technology and brings several novelties in respect to the current state-of-the-art.
Abstract: Recently the conservative space industry driven by the requirements of novel applications decided to introduce multiprocessor systems. Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance. The chip has special power supply architecture with 13 power domains and Adaptive Voltage Scaling (AVS) mechanism based on voltage regulators which imposes a non-standard IC design flow. The measurement results showed that the power supply of the multiprocessor cores can be reduced from the nominal 1,2 V downto 0,82 V without compromising power integrity.

12 citations


Proceedings ArticleDOI
W. T. Chen1, C. C. Lin1, C.H. Tsai1, H. Hsia1, Kai-Yuan Ting1, Shang-Yun Hou1, C. T. Wang1, Douglas Yu1 
03 Jun 2020
TL;DR: These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.
Abstract: A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of the CoWoS provides the capacitance density of 300 nF/mm2 and low leakage current of <1 fA/μm2. The impact of the DTC on power integrity of the logic-HBM2E system is investigated. In the logic core area, the system power delivery network (PDN) impedance and the 1st voltage droop for the CoWoS with the DTC are 93% and 72% lower than those without the DTC. For the HBM2E PHY area, the PDN impedance and simultaneously switching noise (SSN) of VDDQ for the CoWoS with the DTC are 76% and 62% lower than those without the DTC. Moreover, 11.2% and 16.6% unit interval (UI) eye margin are obtained at the data rate of 2.8 and 3.2 Gbps, respectively. These demonstrate the new CoWoS platform with the DTC provides superior power integrity (PI) performance and greatly enhances the system performance for the next generation artificial intelligence (AI) and HPC applications.

12 citations


Journal ArticleDOI
TL;DR: The proposed model relies on the use of state-aware weighting functions that control the transitions of the driver’s output stage for the scenarios where switched input logic states are shorter than the preemphasis duration, and the influence of supply voltage variation is considered.
Abstract: This article addresses the nonlinear behavioral modeling of tunable drivers with preemphasis including power supply noise. The proposed model relies on the use of state-aware weighting functions that control the transitions of the driver’s output stage for the scenarios where switched input logic states are shorter than the preemphasis duration, and the influence of supply voltage variation is considered. For the power supply noise analysis, the method is applied to multiple ports. Feedforward neural networks (FFNNs) are used to implement the state-aware weighting functions, and recurrent neural networks (RNNs) are used to capture the dynamic memory characteristics of driver’s ports. For tunable drivers in the state-of-the-art design covering features such as drive strength and preemphasis, a parameterized model that considers driver control parameters is presented. As a black-box approach, the resulting model protects intellectual property (IP). Practical industrial driver examples demonstrate the good accuracy, flexibility, and significant simulation speedup of the proposed model, which can facilitate the signal and power integrity (SIPI) analysis.

10 citations


Proceedings ArticleDOI
03 Jun 2020
TL;DR: The power integrity (PI) performance gain of the proposed ISC solution was analyzed by applying it to the advanced package platforms such as 2.5D silicon interposer, fanout (FO) package, RDL interPOSer, and substrate based chiplet.
Abstract: An integrated stack capacitor (ISC) solution, which can effectively suppress power noise in high frequency bands, is introduced. The basic structure of the ISC is a vertical cylinder array consisting of many capacitive vias. The proposed ISC shows high capacitance density compared to the existing silicon capacitors. In this study, the power integrity (PI) performance gain of the proposed ISC solution was analyzed by applying it to the advanced package platforms such as 2.5D silicon interposer, fanout (FO) package, RDL interposer, and substrate based chiplet. Based on 3D wafer on wafer (WoW) technology, ISC is a not only 2.5D silicon interposer for high performance computing (HPC) and server that operates with high power, but also a novel silicon capacitor solution that can be applied to substrate and fanout packages for mobile and automotive.

9 citations


Journal ArticleDOI
TL;DR: In this paper, a physics-based circuit modeling methodology for system-level power integrity (PI) analysis and design is presented, which is based on representing the current paths in the power distribution network (PDN) with appropriate circuits based on cavity model and plane-pair partial element equivalent circuit (PEEC).
Abstract: A physics-based circuit modeling methodology for system-level power integrity (PI) analysis and design is presented herein. The modeling methodology is based on representing the current paths in the power distribution network (PDN) with appropriate circuits based on cavity model and plane-pair partial element equivalent circuit (PEEC). The PDN input impedance looking from on-chip sources can be computed. A commercial simulation tool is used to corroborate the modeling approach where the system consists of a commercial integrated circuits, a complex organic package and a very high-layer-count printed circuit board. Two types of circuit models are proposed from the methodology with physical correspondence maintained in the circuit elements. The circuits can be used to analyze the geometry impact on the PDN impedance and explore design improvements. Voltage ripple simulations are conducted with the circuit models. The simulated results correlated with measurements. The modeling methodology helps to understand the impact of the fundamental physics of the different parts of the PDN system and the impact of changes in the PI designs.

9 citations


Proceedings ArticleDOI
Jisoo Hwang1, Hoi-Jin Lee1, Hyun-Jong Lee1, Heeseok Lee1, Min-Kyu Kim1, Youngmin Shin1 
03 Jun 2020
TL;DR: In this article, the methods for improving the power integrity of low power SOC (System-On-Chip) are discussed, and it is confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM.
Abstract: In this paper, the methods for improving the PI (Power Integrity) of low power SOC (System-On-Chip) are discussed. In order to confirm the PI improvement effect by using MIM (Metal-Insulator-Metal), system-level PDN impedance and voltage drop was analyzed for cores with one LICC (Low Inductance Ceramic Capacitor) embedded in the package. Compared to the case where no decoupling capacitor was applied, the PI characteristics were improved when the LICC (Low Inductance Ceramic Capacitor) was inserted in the package substrate, and more dramatic improvement can be achieved by using MIM. When the embedded decoupling capacitor and the MIM capacitor corresponding to the core area are used at the same time, the system-level PDN impedance is reduced by less than half compared with the case where only the embedded LICC is used. Also, it was confirmed by simulation and measurement that voltage drop and voltage ripple can be reduced by implementing MIM. In particular, MIM has been analyzed to be more effective at high frequencies than conventional ceramic capacitors, making it a suitable PI improvement solution for the beyond Moore era.

7 citations


Proceedings ArticleDOI
26 Feb 2020
TL;DR: In this article, a surrogate-based optimization (SBO) method, including space mapping (SM), is applied to efficiently tune equalizers in HSIO links using lab measurements on industrial post-silicon validation platforms, speeding up the PHY tuning process while enhancing eye diagram margins.
Abstract: Enhancing signal integrity (SI) and reliability in modern computer platforms heavily depends on the post-silicon validation of high-speed input/output (HSIO) links, which implies a physical layer (PHY) tuning process where equalization techniques are employed. On the other hand, the interaction between SI and power delivery networks (PDN) is becoming crucial in the computer industry, imposing the need of computationally expensive models to also ensure power integrity (PI). In this paper, surrogate-based optimization (SBO) methods, including space mapping (SM), are applied to efficiently tune equalizers in HSIO links using lab measurements on industrial post-silicon validation platforms, speeding up the PHY tuning process while enhancing eye diagram margins. Two HSIO interfaces illustrate the proposed SBO/SM techniques: USB3 Gen 1 and SATA Gen 3. Additionally, a methodology based on parameter extraction is described to develop fast PDN lumped models for low-cost SI-PI co-simulation; a dual data rate (DDR) memory sub-system illustrates this methodology. Finally, we describe a surrogate modeling methodology for efficient PDN optimization, comparing several machine learning techniques; a PDN voltage regulator with dual power rail remote sensing illustrates this last methodology.

7 citations


Journal ArticleDOI
TL;DR: An EBG structure for power distribution network is optimized with the presented GA method to improve the performances of power integrity and agreements between the measured results and the simulation ones are observed.
Abstract: In this paper, an improved genetic algorithm (GA) for automatically optimizing electromagnetic bandgap (EBG) structure with good power integrity performance is presented. The traditional GA is improved in several ways including Hamming Distance initialization, elite selection and non-repeating crossover, which can generate initial population charactering solution space in detail, increase crossover efficiency, and accelerate convergence. Furthermore, an EBG structure for power distribution network is optimized with the presented GA method to improve the performances of power integrity. The simultaneous switching noise propagation can be prohibited from 0.38 GHz to 20 GHz with a suppression level of -60 dB. Good agreements between the measured results and the simulation ones are observed.

5 citations


Proceedings ArticleDOI
03 Jun 2020
TL;DR: In this paper, PI (Power Integrity) performance of interposer package-on-package (POP) is analyzed with respect to types of package decoupling capacitors and relative location of package DECs to CPU and PDN (Power Distribution Network) of package.
Abstract: In this paper, PI (Power Integrity) performance of interposer package-on-package (POP) is analyzed with respect to types of package decoupling capacitors and relative location of package decoupling capacitors to CPU (Central Processing Unit) PDN (Power Distribution Network) of package. Packages with the decoupling capacitor within SOC package substrate, and that on bottom ball land side are being analyzed and compared in terms of system-level core PDN impedance. Moreover, decoupling capacitor’s placement with respect to that of CPU cores are being analyzed. In addition to the PI performance improvement of the package using decoupling capacitor, the system-level PI performance were analyzed and improved through co-optimization of on-chip PDN.

Proceedings ArticleDOI
03 Jun 2020
TL;DR: This paper proposes weighted cost function that can consider thermal and power delivery together, and gives promising improvements of peak temperature with a reduced overhead in power delivery.
Abstract: Heat removal and power integrity have become major concerns in floor-planning of heterogeneous multi core in system on a chip (SOC). Heterogeneous multi core brings new challenges to balance thermal and power point of view because optimal floor-plan is different for each perspective. This paper proposes weighted cost function that can consider thermal and power delivery together. We discuss methodology for cost function formulation covering multi-physics. The case study of SOC having 8 cores CPU was presented to illustrate our approach. Thermal and power delivery analysis result shows difference result for each perspective, but after converting thermal and PI characteristics improvement into package cost by multiplying their improvement and package cost per improvement, we could figure out the best floor-plan having minimum cost is thermally best floorplan because the majority of cost was originated from thermal characteristics. Finally, our approach gives promising improvements of peak temperature with a reduced overhead in power delivery.

Journal ArticleDOI
TL;DR: In this paper, an approach for power integrity analysis on multi-layer printed circuit boards is presented, where inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance.
Abstract: An approach is presented for power integrity analysis on multi-layer printed circuit boards in this paper. Two critical current paths are analyzed. Inductance decomposition is applied to identify the critical parameters that can influence the PDN input impedance. Two types of stack-ups are used to perform sensitivity analysis to illustrate the effectiveness of PDN design guidelines. Based on the analysis of the inductance contribution from different blocks in the PCB PDN, a systematic approach to obtain a complete understanding of PDN behavior is proposed. The approach can be used to provide design guidance in PDN design practice.

Proceedings ArticleDOI
14 Dec 2020
TL;DR: A Newton-Raphson (N-R) based method is developed for performance evaluation of power delivery networks with arbitrarily shaped parallel-plate power/ground plane pairs and the results are observed in good agreement with those obtained from a numerical electromagnetic (EM) simulator.
Abstract: A Newton-Raphson (N-R) based method is developed for performance evaluation of power delivery networks (PDN) with arbitrarily shaped parallel-plate power/ground plane pairs. The proposed method allows for PI assessment in a few iteration steps while providing significant computational efficiency compared to alternative methods. The proposed method is tested on a practical example and the results are observed in good agreement with those obtained from a numerical electromagnetic (EM) simulator.

Proceedings ArticleDOI
01 Oct 2020
TL;DR: In this article, the authors conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time.
Abstract: The optimal selection of an interposer substrate is important in 2.5D systems, because its physical, material and electrical characteristics govern the overall system performance, reliability and cost. Several materials have been proposed that offer various tradeoffs including silicon, organic, glass and etc. In this paper, we conduct a quantitative comparison between two 2.5D IC designs based on silicon vs. liquid crystal polymer (LCP) interposer technologies in the overall system level for the first time. We also investigate tradeoffs in power, performance and area (PPA), signal integrity (SI) and power integrity (PI) depending on the interposer technologies. Through our flow, we generate a large-scale benchmark architecture with commercial-grade GDS layouts of interposer and chiplets using two different interposer substrates. Then, we model transmission lines and power delivery network (PDN) of each 2.5D IC design. Finally, we perform PPA analysis, SI and PI on both 2.5D IC designs to observe the quantitative tradeoffs between two designs. Our experiment shows that silicon interposer-based design has 10.46% less power, 0.25× smaller area and 0.57× shorter average wirelength compared to LCP interposer-based design. However, LCP-based design has 0.59× smaller PDN DC impedance and 0.75× shorter worst delay of interposer wire while maintaining the power delivery efficiency. Lastly, our cost analysis of 2.5D IC design indicates that the overall cost of organic LCP technology, if both the chiplets and their interposer costs are combined, is 2.69× higher than the silicon even the cost of LCP interposer is 1.91% of silicon interposer. This indicates that LCP technology is prohibitive unless the interconnect and bump dimensions are dramatically reduced.

Proceedings ArticleDOI
03 Jun 2020
TL;DR: The authors present power integrity (PI) and thermally enhanced a new Si-based capacitor promising low ESL, high density capacitance and low z-profile form-factor, which is implemented by employing the legacy fabrication process which had been used for high density capacitor cell in DRAM.
Abstract: As system on chip (SOC) has evolved to integrate more functions in semiconductor integrated circuit (IC), the market needs more advanced wafer fabrication technology which can implement low power system. With this change, the voltage fluctuation problem of low power has been more and more critical so, the engineers had tried to find effective solution to resolve the power delivery issue. Chip capacitors had been placed onto surface of substrate firstly, and capacitors had been moved into substrate for embedding with some applications to reduce the distance between SOC die and capacitor, resulted in performance improvement of power. But, impedance reducing of voltage has been remaining issue as the operating frequency of IC has been increased dramatically. Several ceramic capacitors for reducing equivalent series inductance (ESL) have been developed to overcome such kinds of issue and also, thin film capacitor has been suggested as another novel approach. Deep trench silicon capacitor based on silicon wafer fabrication processing technology has been utilized as one of effective way for device performance improvement. The authors present power integrity (PI) and thermally enhanced a new Si-based capacitor promising low ESL, high density capacitance and low z-profile form-factor, which is implemented by employing the legacy fabrication process which had been used for high density capacitor cell in DRAM (dynamic random access memory). We had noticed that the proven technology in DRAM products could be one of the best solution to make extremely low ESL capacitor. One of the most critical factors to determine the product success of mobile device is to achieve the competitive form factor including package height. This ultra low ESL capacitor is also very effective solution to make ultra thin profile capacitor and competitive package height eventually without sacrificial of capacitance at all. Here, we provide the comparative study of ultra low ESL silicon capacitor and conventional ceramic capacitor with substrate embedded platform for mobile SOC products. Power Delivery Network analysis based on the various structure and design options will be provided. In terms of ESL of capacitor and Z of PDN, while the low ESL ceramic capacitor called by LICC has ESL larger than 60 pH, the presented Si-based capacitor has ESL smaller than 3pH, which eventually reduces the peak value in self-impedance of PDN by 50%. Thermal performance analysis is performed also with various scenarios of mobile applications. With the electrical and thermal performance simulation analysis, the impact of new technology presented in this work on voltage drop of SOC package will be demonstrated through performance measurement evaluation finally. Actual SOC product for premium smartphone with package on package (POP) format will be used for the evaluation.

Proceedings ArticleDOI
03 Jun 2020
TL;DR: This paper details how electrical co-optimization of the silicon-package interaction, was achieved through a coupled circuit-to-electromagnetic modeling and simulation methodology and laboratory measurements on a 16-channel ultrasound pulser circuits are presented that validate the integrity of the co-design modeling and Simulation methodology.
Abstract: The drive for highly integrated ultrasonic scanners electronics stems from the ever-increasing demand for portable, high-quality miniaturize ultrasound imaging systems. Integration drives design complexities due to increase electromagnetic interactions of circuit and package. As such, signal and power integrity issues are exacerbated with impact to system performance, if not considered and addressed early in the design phase. In this paper we present the package electrical co-design and measurement validation results of a highly integrated, high- performance transmitter solution for ultrasound imaging system. We detail how electrical co-optimization of the silicon-package interaction, was achieved through a coupled circuit-to-electromagnetic modeling and simulation methodology. Laboratory measurements on a 16-channel ultrasound pulser circuits (PULS) are presented that validate the integrity of the co-design modeling and simulation methodology.

Proceedings ArticleDOI
23 Sep 2020
TL;DR: The investigate on the via impedance control is studied to optimize the via design on the pitch, individual and oval antipad shapes and the further analyses of via design parameters are examined to understand the effects of dominance.
Abstract: As the technology continues scaling down and the data rate is increasing dramatically, PCB design has become more challenging than ever. Keeping track of signal and power integrity becomes a requirement for PCB designers in order to meet the product development time and reduce the overall cost. In high speed IO signals, vias play a critical role for the signal integrity quality. It is important to design the via impedance within a certain range. Due to server products have a higher thickness of PCB design than other consumer products, and its data rates are on the cutting edge, the need for the via optimization is acquired. In this work, the investigate on the via impedance control is studied to optimize the via design on the pitch, individual and oval antipad shapes. And the further analyses of via design parameters are examined to understand the effects of dominance.

Proceedings ArticleDOI
Mincent Lee1, Cheng-Tse Lu1, Chia-Heng Tsai1, Hao Chen1, Min-Jer Wang1 
01 Sep 2020
TL;DR: A new flow with machine learning methodologies to detect previously ignored anomalies on site-aware wafer-maps for predictive maintenance to complete the high-quality and cost-effective test methodology with test defense.
Abstract: This paper introduces an anomaly detection methodology with machine learning for Circuit Probing (CP) using Integrated Passive Device (IPD) as example devices. The IPD can improve the power integrity, performance, and package dimensions of the Integrated Fan-Out Package on Package (InFO-PoP), which is more cost-effective than 3D Integrated Circuits (3DIC) to achieve “More than Moore’s law” for mobile devices. Because a defective IPD can invalidate the entire package, the previous test methods are dedicated to very high-end screening for the underkill/failure-escape of high quality and reliable devices. On the other hand, the overkill issues are not concerned yet, which periodically impact the yield and cost. In this paper, we propose a new flow with machine learning methodologies to detect previously ignored anomalies on site-aware wafer-maps for predictive maintenance. The proposed flow covers the overkill and re-test issues to complete the high-quality and cost-effective test methodology with test defense.

Proceedings ArticleDOI
14 Dec 2020
TL;DR: In this article, the importance of power delivery network (PDN) with minimal level of impedance on the printed wiring board (PWB) with multi-Gigabit signal transmission and the effect of embedded capacitance material (ECM) in reducing the PDN impedance across the wideband range.
Abstract: This paper discusses the importance of power delivery network (PDN) with minimal level of impedance on the printed wiring board (PWB) with multi-Gigabit signal transmission and the effect of embedded capacitance material (ECM) in reducing the PDN impedance across the wideband range. The advantages of applying ECM versus discrete decoupling capacitors on compact PWB in terms of physical real estate and power integrity are also introduced. The work to investigate the feasibility of ECM substituting the discrete decoupling capacitors was implemented in two stages. In the first stage, the power integrity simulation was performed to analyze the PDN impedance of the power net of interest. In the second stage, the physical measurement of simultaneous switching noise (SSN) of the power rail of interest and the eye diagram of the Peripheral Component Interconnect express (PCIe) signal at 2.5 Gbps are carried out using oscilloscope. The jitter and SSN are diminished by 19 % and 9.3 % respectively when the PWB is laminated with ECM. Hence, the ECM is capable to serve as an alternative to the decoupling capacitors and facilitates the miniaturization of the PWB.

Proceedings ArticleDOI
25 Mar 2020
TL;DR: An in-depth evaluation of the impacts of process and temperature variations on HVR is presented and a systemic solution to incorporate variation awareness into the HVR system control policy is proposed to add up to 4.28% in system power efficiency with minimal hardware overhead.
Abstract: Large-scale systems-on-a-chips (SoCs) have stringent power requirements to ensure adequate supply of power to on-die devices and prevent catastrophic timing violations. Heterogeneous voltage regulation (HVR) leveraging a combination of on-chip and off-chip voltage regulators has been advocated for ensuring power integrity with maximum efficiency. However, unavoidable process and temperature variations have not been considered in prior HVR work. In this paper, we present an in-depth evaluation of the impacts of process and temperature variations on HVR. Furthermore, we propose a systemic solution to incorporate variation awareness into the HVR system control policy to add a further improvement of up to 4.28% in system power efficiency with minimal hardware overhead.

Journal ArticleDOI
TL;DR: It is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.
Abstract: As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.

Proceedings ArticleDOI
17 May 2020
TL;DR: Design tips considering power integrity (PI) for the power distribution network (PDN) in an re-distribution layer (RDL) demonstrate that the PI issues of an RDL can be avoided at an early stage of the chip-package co-design.
Abstract: In this paper, the design tips considering power integrity (PI) for the power distribution network (PDN) in an re-distribution layer (RDL) are presented. First, the methodology of chip-RDL co-simulation is introduced. It indicates that decreasing the PDN loop inductance is critical for a robust PDN design in a high-speed transmission channel. Then, the loop inductance based on a simplified PDN model is derived, which reveals several possible ways to reduce the voltage ripple between power/ground terminals. Finally, the PDN design tips are proposed and verified based on the derived results. These design tips demonstrate that the PI issues of an RDL can be avoided at an early stage of the chip-package co-design.

Proceedings ArticleDOI
15 Sep 2020
TL;DR: This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application and shows how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors.
Abstract: In the most advanced automotive applications, where high frequency signals, design density, high pin-count, miniaturization and integration dominate the scene, the use of Ball Grid Array (BGA) package is necessary to guarantee an excellent performance of devices. This is possible thanks to the higher design flexibility and the compatibility with advanced interconnection technologies like Flip Chip (FC), that allow shorter overall connections inside IC–Package systems. In this context, the trade-off between performance and production costs must be deeply analyzed, in order to drive the choice of materials and technologies to be used for substrates, which represent a significant cost factor in laminate-based packages. This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application. The applied technology combines Flip Chip Solder Bump (FCSB) and High Density Interconnect (HDI) substrate, that uses blind and buried vias. The comparison involves multiple aspects, starting from pre-layout analysis, to the different strategies used during the design implementation, to the Signal Integrity (SI) and Power Integrity (PI) electrical performance. In this field of applications, packages with at least 4-layer substrates are recommended in order to use an optimized microstrip signal-routing with a solid ground reference and dedicate one metal layer to the different power domains. This design strategy helps both SI and PI efficiency. However, 6-layer substrates, despite the additional cost, give a further improvement: for high density signal-routing, the higher flexibility in terms of layers assignment allows an efficient stripline configuration. This leads to enhanced SI parameters (Insertion and Reflection Losses, Crosstalk), while keeping similar advantages in terms of PI. In this analysis, it will also be shown, for both substrates, how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors. The results of SI and PI that will be discussed are obtained by electrical simulations: this permits to quantify the differences between the design strategies considering the operating frequencies of the DDR3 interface.

Proceedings ArticleDOI
12 Oct 2020
TL;DR: A Python tool is described here to enable a fast and configurable process for distributed port assignment during the PDN extraction process, and an enhanced automation flow, integrated with the Python tool, has also been developed to support early power network exploration.
Abstract: The stringent requirements of power noise on complex multi-domain power delivery networks (PDN), and the complicated relationship between signal integrity and power integrity (PI) have led to an ever challenging PI sign-off process. A lumped PDN model is widely used, where the power network is treated as a two-port network with the impedances extracted by an electromagnetic solver. A distributed model of the power network is however preferred during a PI sign-off flow, providing a more accurate circuit model for time domain simulations. Hundreds or even thousands of ports need to be properly evaluated during the PDN extraction process, which can be computationally expensive and error prone. A Python tool is described here to enable a fast and configurable process for distributed port assignment during the PDN extraction process. An enhanced automation flow, integrated with the Python tool, has also been developed to support early power network exploration. In one case study, a 360X speedup in the port assignment process is achieved while revealing a high risk power network within the package. The proposed automation flow is versatile and highly adaptive for different power network topologies.

Proceedings ArticleDOI
01 Aug 2020
TL;DR: This research takes an actual DDR3 controller package design as the background, and the chip adopts advanced packaging collaborative design, including die-package-PCB collaboration design and design-simulation collaboration design.
Abstract: In order to meet people's demand for multi-function and miniaturization of electronic products, the integration degree of electronic products is constantly improving and the speed is getting faster and faster. The research takes an actual DDR3 controller package design as the background. And the chip adopts advanced packaging collaborative design, including die-package-PCB collaboration design and design-simulation collaboration design. Packaging is evaluated in terms of electrical integrity, thermal mechanical properties, manufacturability, testability and so on during package.

Proceedings ArticleDOI
01 Oct 2020
TL;DR: In this paper, the authors proposed a DNN workload-aware dynamic power delivery network (PDN) control policy to maximize system energy efficiency while ensuring power integrity for systolic array-based DNN accelerators.
Abstract: With the growing performance and wide application of deep neural networks (DNNs), recent years have seen enormous efforts on DNN accelerator hardware design for platforms from mobile devices to data centers. The systolic array has been a popular architectural choice for many proposed DNN accelerators with hundreds to thousands of processing elements (PEs) for parallel computing. Systolic array-based DNN accelerators for datacenter applications have high power consumption and nonuniform workload distribution, which makes power delivery network (PDN) design challenging. Server-class multicore processors have benefited from distributed on-chip voltage regulation and heterogeneous voltage regulation (HVR) for improving energy efficiency while guaranteeing power delivery integrity. This paper presents the first work on HVR-based PDN architecture and control for systolic array-based DNN accelerators. We propose to employ a PDN architecture comprising heterogeneous on-chip and off-chip voltage regulators and multiple power domains. By analyzing patterns of typical DNN workloads via a modeling framework, we propose a DNN workload-aware dynamic PDN control policy to maximize system energy efficiency while ensuring power integrity. We demonstrate significant energy efficiency improvements brought by the proposed PDN architecture, dynamic control, and power gating, which lead to a more than five-fold reduction of leakage energy and PDN energy overhead for systolic array DNN accelerators.

Proceedings ArticleDOI
03 Nov 2020
TL;DR: In this paper, the authors explore a couple of methodologies of on-chip power delivery network (PDN) modeling, and provide a flexible and accurate simulation flow for power-aware timing analysis.
Abstract: As the speed of advanced memory products exceeding multi-GHz range, signal integrity (SI) and power integrity (PI) analysis becomes imperative to ensure robust timing performance. This paper will explore a couple of methodologies of on-chip power delivery network (PDN) modeling, and provide a flexible and accurate simulation flow for power-aware timing analysis. Power supply induced jitter (PSIJ) will be examined for 8Gbits LPDDR5 mobile products with a data rate up to 6400Mbps using 1y-nm DRAM process. Package and SoC (system-on-chip) co-simulation can be included as well to extend the PI analysis into system level.

Journal ArticleDOI
TL;DR: In this article, a domain decomposition method (DDM) with a novel modeling of the DGS-EBG-based PDN is presented, and analytical models for the partitioned parts of the PDN are developed, and their impedance parameters are analytically extracted.
Abstract: In this paper, we present the power integrity analysis of a power distribution network (PDN) employing a segmentation technique based on the electromagnetic bandgap (EBG) structure with a defected ground structure (DGS). For efficient analysis of power integrity, a domain decomposition method (DDM) with a novel modeling of the DGS–EBG-based PDN is presented. In the DDM, analytical models for the partitioned parts of the PDN are developed, and their impedance parameters are analytically extracted. The resonant modes for the power integrity analysis are rigorously examined using the DDM and electric-field distribution. The effect of the DGS–EBG stopband on the resonant modes are analyzed. The proposed DDM and power integrity analysis are verified using full-wave simulation and measurements. The DDM result shows good agreement with the full-wave simulation and measurements.

Patent
01 Dec 2020
TL;DR: A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, including a plurality of units, at least one capacitor, and an encapsulant encapsulating the integrated circuit and the at least 1 capacitor.
Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip.