Showing papers on "Power integrity published in 2021"

State Trajectory Control of Startup for LCC Resonant Converters With Capacitive Output Filter

Abstract: LCC resonant converters have been widely adopted in pulse-modulated high-voltage generators to achieve high power density and high efficiency, which require a short rising time of output voltage. However, if the LCC resonant converter starts up too fast, the voltage and/or current stresses of the resonant tank during startup may be several times higher than those of the steady state due to the complex dynamic behavior of the resonant tank. In this article, a simplified state model of LCC resonant converters is first introduced. Then, optimal state trajectory control (OTC) is proposed to optimize the startup performance of LCC converters. Besides, to combine the advantages of OTC in the startup and power integrity (PI) control in the steady state, hybrid control is adopted. Finally, an LCC resonant converter prototype is constructed to verify the proposed OTC, which achieves a minimal rising time of output voltage with no additional current and/or voltage stresses in the resonant tank during startup compared to the conventional control.

SI/PI-Database of PCB-Based Interconnects for Machine Learning Applications

Abstract: A database is presented that allows the investigation of machine learning (ML) tools and techniques in the signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) domains. The database contains different types of printed circuit board (PCB)-based interconnects and corresponding frequency domain data from a physics-based (PB) tool and represent multiple electromagnetic (EM) aspects to SI and PI optimization. The interconnects have been used in the past by the authors to investigate ML techniques in SI and PI. However, many more tools and techniques can be developed and applied to these structures. The setup of the database, its data sets, and examples on how to apply ML techniques to the data will be discussed in detail. Overall 78961 variations of interconnects are presented. By making this database available we invite other researchers to apply and customize their ML techniques using our results. This provides the possibility to accelerate ML research in EMC engineering without the need to generate expensive data.

Enhancing On-die PDN for Optimal Use of Package PDN with Decoupling Capacitor

Abstract: In this paper, a method of enhancing the performance of on-die Power Distribution Network (PDN) and modeling of off-die PDN to utilize a maximum of package-level PDN solutions with decoupling capacitor have been proposed. To improve the on-die PDN performance, multi-stacked Cu-pillar bump RDL is provided for tighter connections between bumps and decoupling capacitor for sharing between switching instances. The proposed multi-stacked Cu-pillar bump RDL is a cost-effective solution to improve on-die PDN performance. However, reinforcing on-die PDN on active layers requires expensive and complex processes. The proposed off-die PDN modeling method can further secure the power integrity performance margin, especially when applying the decoupling capacitors. It is proposed to consider only the ground bumps in the IP area as the reference for power domain to which the decoupling capacitor is applied. This helps in revealing the potential PDN design issues of the IP.

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP

Abstract: Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last assembly manufacturing availability. To date, the laminate-substrate based interposer-PoP has been employed for high-end mobile APs with very high-volume production. Recently, this interposer-PoP design has faced some technical limitations including the need to reduce: top and bottom routing layer thickness, copper (Cu) trace line/space and via size for next generation mobile APs. These reductions may require ultra-thin package z-height and high-bandwidth bottom and top routing layers. To address these challenges, a new interposer-PoP with High-Density Fan-Out (HDFO) redistribution layer (RDL) routing layer has been designed and demonstrated. It is part of an initiative to achieve an ultra-thin package z-height, interposer-PoP structure with high bandwidth and improved signal integrity/power integrity (SI/PI) routing layer using a chip-last assembly manufacturing process flow. This paper will discuss package-level characterizations on the interposer-PoP with HDFO RDL routing layer as well as package z-height evaluation, temperature-dependent package warpage measurements and package-level reliability tests conducted in accordance with JEDEC.

Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation

Abstract: Spiking neural networks (SNNs) have emerged as a new generation of neural networks, presenting a brain-inspired event-driven model with advantages in spatiotemporal information processing. Due to the need for high power consumption of compute-intensive neural accelerators, adequate power delivery network (PDN) design is a key requirement to ensure power efficiency and integrity. However, PDN design for SNN accelerators has not been extensively studied despite its great potential benefit in energy efficiency. In this paper, we present the first study on dynamic heterogeneous voltage regulation (HVR) for spiking neural accelerators to maximize system energy efficiency while ensuring power integrity. We propose a novel sparse-workload-aware dynamic PDN control policy, which enables high energy efficiency of sparse spiking computation on a systolic array. By exploring sparse inputs and all-or-none nature of spiking computations for PDN control, we explore different types of PDNs to accelerate spiking convolutional neural networks (S-CNNs) trained with the dynamic vision sensor (DVS) gesture dataset. Furthermore, we demonstrate various power gating schemes to further optimize the proposed PDN architecture, which leads to a more than a three-fold reduction in total energy overhead for spiking neural computations on systolic array-based accelerators.

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

Abstract: The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and temperature (PVT) variations in sub-nanometer DRAM process are required to improve performance. To achieve 24Gb/s/pin on a 1.35V DRAM process, this work proposes a GDDR6 DRAM with a half-rate clocking architecture and optimized I/O.

AAA Algorithm for Rational Transfer Function Approximation With Stable Poles

Abstract: Signal and power integrity analysis in time-domain requires suitable models for interconnects and power distribution networks, which are often available only in terms of their frequency responses from electromagnetic simulations or measured data. A rational transfer function approximation of such data allows its integration in circuit simulators. Recently the AAA (adaptive Antoulas-Anderson) algorithm has been introduced for rational function approximation. This letter introduces a modification of that algorithm for fitting in terms of the squared variable ( $s^{2}$ ), called AAA2 algorithm, for generating rational transfer functions with stable poles from frequency response available from simulated or measured data.

A Comparative Study of On-Chip CMOS S&H Voltage Sensors for Power Integrity: SOI vs. Bulk

Abstract: This paper evaluates the performance of two on-chip sample & hold (S&H) voltage sensors, usable for power integrity measurements, with the aim to compare silicon-on-insulator (SOI) & bulk CMOS technologies. Both sensors were designed and simulated in 180 nm 5 V AMS-bulk and XFAB-SOI processes, using optimized parameters and compatible devices. The fundamental variables analyzed were power consumption, leakage current, slew rate (SR), and transient output voltage, under process, voltage and temperature variations. Compared to bulk technology, SOI was found to have lower power consumption (by 2.2 mW in average) and leakage supply current (by 9.5 pA at 27○C), higher sensitivity to process variations (up to 88% additional slew rate versus 39% at 80○C), higher resilience to temperature changes (6% in output voltage), and a larger occupied area. The SOI sensor is intended to be fabricated and used to evaluate injected continuous wave and transient disturbances as well as voltage fluctuations due to internal activity on power distribution networks.

A novel multi-chip stacking technology development using a flip-chip embedded interposer carrier integrated in fan-out wafer-level packaging

Abstract: Traditional heterogeneous integrated package structure actually uses several complete IC packages, while the final heterogeneous integrated package structure is completed by restacking and packaging of various IC packages. However, the relatively large package volume, low-density interconnections and low circuit density cannot meet the demand for lighter products. There are still many issues remained in the heterogeneous integration process due to the fact that each chip has its own chip size, material properties, and device type. In order to integrate various heterogeneous chips, a new chip stacking technology is necessary to simplify and reduce the packaging structure, which is used for multi-chip and multi-layer heterogeneous integrated packaging structures as well as obtaining high performance and high bandwidth density. A novel EIC (Embedded interposer carrier) heterogeneous integrated packaging technology is developed to provide SOC-like multi-layer and multi-chip stacking capabilities, which is similar to chiplet concept. In this work, a 21-mm × 14-mm interposer is embedded into an electric package, allowing the interposer to work as a bridge between the two chips, and to provide high-density and high-pin-count interconnects. The external dimension of these two chips is 9 mm × 9 mm and the chip thickness is 100µm. The electrical performance including the power integrity/signal integrity analysis was evaluated by designed test patterns. Daisy chain and Kelvin structure were also included in the testing structure. This new packaging structure is compatible with fan-out packaging technology and enables integration for different chips in order to achieve performance related to 3D IC with a low cost.

Optimal Power Distribution Network Design for High-Performance Solid-State-Drive Based on Novel Target-Impedance Extraction Method

Abstract: In this paper, we proposed a novel methodology to offer power distribution network (PDN) design guide for PCB power integrity (PI) design for high performance solid-state-drive (SSD). Compared with conventional target-impedance (Z) formulated by current profile of a chip power model (CPM), the proposed methodology utilizes a measurement based current spectrum and a hierarchical PDN-Z model. In order to solve the fundamental limitations of the narrow-banded CPM current model, we successfully measured the PCB-level current of memory packages consisting of the SSD device and converted the measured current values to the chip-level current values using Y-matrix of the hierarchical PDN-Z model consisting of a PCB, a test interposer, a package, and a chip. High-capacity SSD devices are too expensive to make PCBs for design of experiments to test device performance with current measurement. Therefore, we made a test interposer to measure cost-efficiently a current spectrum for each specific power-domain of a unit package such as a DRAM, a NAND, and a SSD controller that all consisting of a SSD device without disturbing SSD’s normal operations.

PI/SI consideration for enabling 3D IC design

Abstract: In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.

Reinforcement Learning-Based Decap Optimization Method for High-Performance Solid-State Drive

Abstract: In this paper, we propose an improved optimal decoupling capacitor (decap) design method based on Q-learning algorithm for high-performance solid-state drive (SSD). The proposed method selects optimal decap combinations that satisfies target impedance with minimum decap number. Based on Q-learning algorithm combined with transmission line theory, optimal decap combinations of power distribution network (PDN) can be provided. The proposed method was verified with voltage ripple measurement and PDN impedance simulation using SSD for high-performance server application. Conventional decap optimization method are using complex and time-consuming analytical tool with power integrity (PI) domain expertise. However, the proposed method requires only the PDN and decap information along with a simple Q-learning model without PI knowledge, providing faster and accurate results than full search optimization method. For example, in 21 decaps combination problem, the proposed method’s computing time consumes only few minutes, 89.09 sec, which is significantly reduced result compared with the conventional full search simulation. Therefore, we expected the proposed method can be widely used to solve for decap optimization problem with complex PDN.

Towards an LTCC SiP for Control System in Safety-Critical Applications

Abstract: This paper presents a compact configurable power control system for safety-critical applications, which operates in harsh environments. This heterogeneous integrated mixed digital, analog and high-voltage design for power applications is implemented in a system-in-package (SiP) module using a low-temperature co-fired ceramics (LTCC) substrate. A comparison between technologies for SiP designs shows that LTCC is advantageous in terms of integration density, thermal and electrical performances, as well as signal and power integrity. In addition, this work proposes layout and fabrication techniques for the enhancement of thermal, electrical performances and integration density specific to LTCC-based designs, such as chip-covering, multi-layer routing of power signals and self-damped transmission lines. An improvement of 59% in available area, 32% reduction of temperature due to self-heating, 65% loss reduction and 22% reduction in interference coupling were obtained when compared to a baseline design.

Solving Power Integrity Challenges for Smart Computing Era

Abstract: To solve increasingly difficult power delivery issue for high-end 2.5D and 3D based smart computing systems, we propose the combined structure of backside PDN and integrated stack capacitor (ISC). Transistor shrinkage continues to deliver the performance needs for AI-enabled smart devices with relatively constant device size causing the power delivery path to be very narrow and resulting a severe IR-drop issue. The concept of backside PDN has recently been proposed to minimize the delivery path and IR drop. To further address AC noise, we propose using backside PDN with ISC. To simplify the analysis, we model the system using a lumped circuit and simulate on both frequency and time domains. In the simulation, we assume the simplest current scenario which assumes step pulse after idle state. ISC can be integrated in 2.5D and 3D systems in three different ways: discrete device, 2.5D silicon interposer, 3D Wafer-on-Wafer (WoW) integration. Our simulation assumes interposer-based ISC with backside PDN for a variety of analysis. As confirmed in the previous researches related to ISC, hundreds of MHz noise is effectively decreased. Applying of backside PDN decreases the voltage drop at the steady state as well.

Power Delivery Network Impedance Profile and Voltage Droop Optimization

Abstract: The design process of power delivery networks (PDN) in modern computer platforms is becoming more relevant and complex due to its relationship with high-frequency effects on signal integrity. When circuits start operating, the changing current flowing through the PDN produces fluctuations creating voltage noise. Unsuccessful noise control can compromise data integrity. A suitable PDN design approach is the use of decoupling capacitors to lower the impedance profile and mitigate current surges, ensuring a small variation in the power supply voltage under significant transient current loads. An optimization approach to determine the number of decoupling capacitors in a PDN is presented in this paper, aiming at decreasing the amount of decoupling capacitors without violating the PDN design specifications, looking at both the impedance profile in the frequency domain and the resulting voltage droop in the transient time-domain.

High-Density Small Form-Factor Package with Polygon-Shaped Capacitor Based on Silicon Technology

Abstract: This paper suggests a unique silicon capacitor shape to provide a very competitive package form-factor with limited height condition. To locate a discrete capacitor on the BGA side of package, some solder balls must be depopulated to secure capacitor mounting space. Also to implement silicon based multi terminal capacitor with fine pitch bumped format, a conventional capillary underfill dispensing keep out zone should be considered. The removed solder balls may affect the system PDN with the decreased power connection or overall X-Y dimension expansion with the increased SOC functionality. To find an optimized shape and size against various BGA arrangement option, it is very important to have a successful product solution. A comparative study of various design concept of normal rectangular and polygonal shape of capacitor on BGA side with respect to area usage efficiency, maximum ball usage, and power integrity performance enhancement for high-density small form-factor package is described in this paper. The number of depopulated solder balls will be increased according to the use of multiple capacitors with rectangular shape. But, it can be optimized with one big polygonal shape and multiterminal of silicon capacitor. Interposer POP package for mobile device will be used as a target package type and the latest structure of substrate and ball pitch will be used for the study to reflect a realistic scenario.

Research on SiP Signal Integrity Based on Ansys SIwave in Wearable Medical Systems

Abstract: One of the main challenge for wearable medical systems is how to integrate more functional ICs in a very small space. As a kind of new packaging and system integration technology, SiP (System in Package) simplifies the system design and complies with the requirements of device miniaturization with multi-component integration. However, high layout and routing density in SiP substrate tend to cause SI (Signal Integrity) and PI (Power Integrity) issues. This paper introduces the main reasons and improvement measures for signal and power integrity issues in SiP designs. Based on ANSYS SIwave simulation platform, the simulation process of major parameters for signal and power integrity and related optimization methods are discussed in the design process of SiP.

Signal and Power Integrity Design Methodology for High-Performance Flight Computing Systems

Abstract: Computing capabilities of space systems have increased onboard performance by orders of magnitude with the use of radiation-tolerant field-programmable gate arrays (FPGA) and processors. The incorporation of signal and power integrity analysis with printed circuit board (PCB) design in reliable computing architectures for space systems has become critical to enable future mission capabilities. Developers launch high-performance processors into a breadth of orbits and missions, running varying applications that create challenges for designing reliable computing hardware. Specifically, for these designs, academic and industry research has focused on component radiation performance, fault mitigation, and reliable architectures. However, other design parameters including electromagnetic interference (EMI), PCB stackup, signal integrity (SI), voltage regulator module (VRM) design, and power distribution network (PDN) are often deprioritized or disregarded as the design matures. Since these characteristics are becoming more significant in high-performance processor designs, this research presents a hardware design and analysis methodology for high-performance, space-computing systems that focuses on a holistic design approach and PDN reliability. While these challenges exist across all space hardware, the reduced PCB dimensions imposed by SmallSats and CubeSats introduce additional hurdles, specifically to VRM and decoupling design. By examining the relationship between the PDN and radiation performance, an analytical relationship is developed that incorporates Total Ionizing Dose and Single-Event Transients to ensure reliability throughout the mission duration. The presented design methodology is applied to the SpaceCube v3.0 Mini, an FPGA-based on-board science data processing system developed at NASA Goddard Space Flight Center.

Decoupling Capacitor Optimization to Achieve Target Impedance in PCB PDN Design

Abstract: With increasingly stringent requirements for lower voltage supply, and higher density in PCB (Printed Circuit) PDN (Power Distribution Network) design, power integrity has an increasingly important role in PCB design. The PI performance of the PCB design must meet requirements, or modification and trial-and-error are necessary to ensure the target impedance is satisfied. Lots of design practices and commercial tools are utilized to aid PI designers, e.g., developing a suitable stack-up, saving cost while placing enough decoupling capacitors, best layout for IC pins and so on. It is essential in the PCB PDN design to place as fewer decoupling capacitors as possible to achieve target impedance and voltage ripple goals while saving cost. In this paper, the influence from the types of decoupling capacitor and stack-up is considered. The variety of decoupling capacitors contributes to the objective of reaching the target with minimum number of decoupling capacitors.

Time Domain Continuous-Time Model of Current Mode Buck Converter for Power Delivery Network Design

Abstract: Proper power integrity (PI) analysis is essential for modem electronics devices to minimize voltage noise. The low- frequency response of a power distribution network (PDN) is determined by the voltage regulator modules (VRMs) installed on the board. However, the conventional VRM model is either represented by an over-simplified passive circuit or an encrypted model provided by then vendor. These models can only work for limited operating conditions. In this paper, a generic average model for up-to-date DC converter is proposed. Both time and frequency domain responses of a current-mode buck converter with adaptive on-time control (AOT) method are captured by the proposed model. This cycle-by-cycle averaged model can be extended for converters with other control methods.

Exploring the Feasibility of Using 3-D XPoint as an In-Memory Computing Accelerator

Abstract: This article describes how 3-D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning (ML), can be implemented within a 3-D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core concept to address issues such as system scalability, where we connect multiple 3-D XPoint arrays, and power integrity, where we analyze the parasitic effects of metal lines on noise margins. To assure power integrity within the 3-D XPoint array during this implementation, we carefully analyze the parasitic effects of metal lines on the accuracy of the implementations. We quantify the impact of parasitics on limiting the size and configuration of a 3-D XPoint array, and estimate the maximum acceptable size of a 3-D XPoint subarray.

Experimental Noise and Signal Analysis on Printed Circuits Board Design

Abstract: The objective of this study was to improve the power noise and eye diagram signal on printed circuits board design. The method was to analyze the transmission signal and improve signal integrity by impedance matching. The power integrity introduces measured power initialization sequence, rails, and timing. The eye diagram of signal improvement from the experimental result was compared for jitter, clock, and voltage noise. The result shows the improvement of the signal transmission on printed circuits board design to achieve optimal signal integrity.

Radio Frequency Interference Due to Power Plane Radiation and Mitigation Using RFI and PI Co-Optimized Design in Mobile Platforms

Abstract: This paper’s main focus is to study the noise radiation risk from motherboard power planes, including the mechanism of power plane radiation. A design for a power plane that is optimized for radio frequency interference (RFI) and power integrity (PI) is studied and simulation and measurement results are presented. This design has been proposed to reduce the level of RFI radiated from the power plane to the nearby antennas.

Impact of Supply Noise on Nano-Meter VLSI Design: Hard or Soft Threshold?

Abstract: With VLSI keeps scaling down, power supply noise margin gets further diminished due to the relatively stable threshold voltage. On the other hand, the continuously growing current density incurs additional supply noise, which easily violates the pre-set power integrity noise margin threshold. Thus, power integrity (PI) designers have to either conduct repeated back-tracking or add additional die area to reduce the unwanted supply noise, which is both cost and time consuming. A very natural question that may arise is then what happens if this noise margin threshold is violated? In this paper, we will investigate the impact of supply noise on various designs for nano-meter VLSI and discuss the potential opportunities that may provide PI designers with additional design flexibility.

A Study on an IBIS-like Model to Ensure Signal/Power Integrity for I/O Drivers

Abstract: This paper presents a study on non-linear modeling, reported in the state-of-the-art in the last decade for I/O drivers. The study includes the IBIS-like modeling techniques including package parasitics. The IBIS-like model has been analyzed mathematically and validated using 28 nm CMOS technology of TSMC foundry. For validation purposes, the predriver circuit and the I/O buffers have been simulated with 0.9 V of VDD. The IBIS-like nonlinear models have been created using Simulink® and the results have been compared with the Electronic Design Automation (EDA) tools. The Simulink® results show a Normalized Mean Square Error (NMSE) of - 51.91 dB with 1.63 sec of CPU time for the case of pull-up current, -49.42 dB with 474.34 msec of CPU time for the case of pulldown current response. In the case of output voltage response, the NMSE is - 48.33 dB and 2.12 sec of CPU time.

Impact of System-in-Package in side-by-side discrete SoC-DRAM configurations on SI, PI and thermal performance

Abstract: In this paper, a SoC (System on Chip) - DRAM configured 2D planar side-by-side SiP (System in Package) is compared to a conventional SCP (single chip package) on board with respect to SI (signal integrity), PI (power integrity), and thermal performance. In SI and PI aspects, eye aperture widths of DQ signals are used as a figure of merit for performance decisions. SiP's shorter channel lengths and fewer discontinuities can result in wider eye apertures but its longer and smaller PDN (power delivery network) shapes narrows them. In order to enhance SiP PI and consequent wider eye aperture width, De-cap (decoupling capacitor) values are swept and their numbers, capacities and locations are changed. Finally, the optimal De-cap placement to achieve robust PI performance can be found. However, since SiP has shorter distance and larger thermal coupling between SoC and DRAM, SiP configuration shows a comparatively worse thermal performance than SCP on board. The thermal comparison is based on two temperatures taken from the top surfaces of the SoC and DRAM, and the leakage power of the two SoC's. Through this comparison study between SCP on board and SiP, a basic understanding on how to adopt advanced DDR features in SiP application for D-TV (digital TV) can be obtained.

Integrated Circuit Characterisation Using Low-Cost Coaxial Probe Measurement

Abstract: This paper presents a method to characterise integrated circuit (IC) using a low cost coaxial probe. The characteristic impedance of the IC can be used in both time and frequency domain, where it significantly improves the behavioral model of a printed circuit board (PCB) circuitry which is currently being used with limited functionality. S-parameter results obtained from the measurement using the coaxial probe was combined in the simulation model of the PCB which was simulated using three-dimensional (3D) full wave simulation. A comparison between the measurement and simulation results was made and it shows that the measured IC characteristic impedance through the devised low cost probe method produces good correlation up to 1,000 MHz. This study concludes that the feasibility of using the proposed technique for impedance characterisation of IC to be included into the PCB circuitry would provide a better understanding of signal and power integrity, and electromagnetic compatibility (EMC).

Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator

Abstract: This paper describes how 3D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning, can be implemented within a 3D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core concept to address issues such as system scalability, where we connect multiple 3D XPoint arrays, and power integrity, where we analyze the parasitic effects of metal lines on noise margins. To assure power integrity within the 3D XPoint array during this implementation, we carefully analyze the parasitic effects of metal lines on the accuracy of the implementations. We quantify the impact of parasitics on limiting the size and configuration of a 3D XPoint array, and estimate the maximum acceptable size of a 3D XPoint subarray.

Study on Power Integrity and Signal Integrity Issues

Abstract: High frequency channel loss, reflection, and crosstalk are causing degradation of the receiver eye opening, jitter performance, and bit error rate. The voltage drop and current density wisely affects the performance of the PCB.The increase in current density in turn increases the temperature of the board which might cause fault in performance or even explosion of the device. In addition, improper PCB design can lead to noncompliance with EMC regulations. The physical design changes required to meet the use case conditions negatively impact the signal and power integrity performance, limiting the speeds and capabilities that are achievable. The signal and power integrity desires directly oppose one another, so a holistic platform design approach is required to optimize system performance. Since power integrity affects the entire device, from the chip to the chip package to the board to the entire system, a variety of factors must be considered to ensure the design.

An On-Chip Clock Generation Circuit for Smart Catheters

Abstract: Cardiovascular diseases are one of the major causes of death worldwide, which drives the research on smart catheters for early diagnosis. Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance, e.g. higher imaging resolution, the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for communication and digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out (LDO) regulator, voltage and current references and a low-jitter digitally controlled oscillator (DCO). The clock generator also comprises a clock divider with programmable duty cycle, allowing system reconfiguration. The circuit is laid out and simulated under application conditions. The LDO achieves a full-spectrum power supply ripple rejection (PSRR) of 50 dB with an output load of 10 mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of −104.5 dBc/Hz at an offset of 1 MHz and 1.25 GHz of oscillating frequency. The proposed clock generator allows digitization at 200 MSps with a maximum SNR of 56.3 dB for an input signal of 50 MHz if phase noise is integrated from 100 kHz to 625 MHz.