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Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.


Papers
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Proceedings ArticleDOI
26 Jun 2007
TL;DR: A process that allows customers to import current profiles from IC tools like VoltageStorm at Cadence, package models obtained from field solver and on-die capacitance to be simulated together to view the impedance in frequency domain and voltage ripples in time domain is introduced.
Abstract: This paper introduces a process that allows customers to import current profiles from IC tools like VoltageStorm at Cadence, package models obtained from field solver and on-die capacitance to be simulated together. The users can view the impedance in frequency domain and voltage ripples in time domain.

3 citations

Journal ArticleDOI
TL;DR: The capability of reacting instantaneously to large voltage droops makes ROCs an attractive solution, which also allows to relax the constraints required for the PDN design, and tolerance to voltage noise and related benefits can be increased with multiple R OCs.
Abstract: Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of power delivery networks (PDNs). Lower supply voltages were made possible with technology scaling, but power density was also increased. Consequently, power integrity became a key factor in the design of reliable high performance circuits. Ring oscillators clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise. However, the effectiveness highly depends on the design parameters of the PDN, power consumption patterns, and spatial locality of the ROC within the clock domain. This paper analyzes the impact of the PDN parameters and ROC location on the voltage noise and the robustness achieved by using ROCs. The capability of reacting instantaneously to large voltage droops makes ROCs an attractive solution, which also allows to relax the constraints required for the PDN design. The experiments show that up to 83% of the margins for voltage noise and up to 27% of the total leakage power can be reduced by using ROCs. In addition, PDN simplifications are possible, with fewer power interconnections or package decoupling capacitors of lower quality. Tolerance to voltage noise and related benefits can be increased with multiple ROCs.

3 citations

Proceedings ArticleDOI
12 Dec 2011
TL;DR: In this article, the authors used a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer, which improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω.
Abstract: Power integrity (PI) for recent electronics circuits and systems is the most important technological issue in the field and has been addressed in important papers through several approaches [1][2]. The latest concept of the best PI condition is recognized as maintaining lower impedance between power and ground lines or planes without any clock frequency dependency, even in the GHz region. We found this concept in a relatively old book [3] from the 1980s; thus, it is not the latest idea. However, it cannot be completely realized by the several previously proposed approaches, including many involving the use of low-inductance capacitances. We are aware that plane power and ground resonance are induced electromagnetic interference(EMI) problems due to resonance caused by eddy currents or multiple reflections of voltage fluctuations. A novel technology was used in our previous study only using a conductive layer of dispersed metal particles [4]. The structure is consisted of a conventional FR-4 printed circuit board in which the copper ground plane was replaced with a metal particle conductive layer [4]. This structure improved the PI for any clock frequency especially in GHz region with an impedance of less than 1 Ω. This improvement is verified by an actual 16-channel 3 Gbps/pin I/O interface board in this study. Even though the simultaneous switching of two sets of 16 drivers gave a fairly high current slew-rate of (8 mA × 32) / 60 ps = 4.27 × 109 A/s, the PI status can be verified by the condition. Result was that PIS structure kept better than Cu plane in the VDD fluctuation.

3 citations

Patent
Chen Peng, Ru Yan, Zhu Wei, Jin Feng, Liao Like 
20 Aug 2014
TL;DR: In this paper, the authors proposed a power distribution network based on a plane C-type bridge electromagnetic band gap structure, where the power plane, the dielectric substrate and the ground plane are sequentially arranged.
Abstract: The invention discloses a power distribution network based on a plane C-type bridge electromagnetic band gap structure The power distribution network comprises a power plane, a dielectric substrate and a ground plane, wherein the power plane, the dielectric substrate and the ground plane are sequentially arranged The power plane comprises an electromagnetic band gap structure unit matrix Each electromagnetic band gap structure unit is of a central symmetry structure and provided with four C-type bridges in a led mode, the four C-type bridges are connected with four adjacent electromagnetic band gap structure units respectively, and the two ends of any C-type bridge are connected to the opposite sides of two adjacent electromagnetic band gap structure units respectively According to the power distribution network, the plane C-type bridge electromagnetic band gap structure units are periodically carved in the power plane of the power distribution network, simultaneous switching noise between the power plane and the ground plane in the power distribution network can be suppressed within a wide frequency range, and the good power integrity of a system can be obtained

3 citations

Proceedings ArticleDOI
01 Sep 2006
TL;DR: In this article, a case study for a typical rectangular power-ground structure was conducted for low-impedance power distribution network design to ensure power integrity as well as signal integrity for high speed packages and printed circuit boards.
Abstract: Design of low-impedance power distribution network is vital to ensure power integrity as well as signal integrity for high-speed packages and printed circuit boards (PCBs). In this paper, we conducted a case study for a typical rectangular power-ground structure. Both analytical and numerical methodologies are used for this purpose. We studied how the impedance of a power-ground structure is affected by the location of the noise injection point, lossy substrate, edge radiation, decoupling capacitors and vias. Conclusions are drawn for this study.

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202312
202267
202139
202045
201965
201852