Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Implementation of power transmission lines to field programmable gate array ICs for managing signal and power integrity

Abstract: As the operating frequencies of electronic devices increase, power and signal integrity have become a major issue Simultaneous switching noise (SSN) is a major problem that restricts the performance of high speed digital systems SSN leads to voltage fluctuations during data transitions which can induce excessive noise SSN is caused by parasitic inductance components in the power delivery network (PDN) that manifest themselves through via transitions, apertures on reference plane, split planes and even solid planes A new method has been proposed to address this problem, which employs power transmission lines (PTL) that supply power to integrated circuits instead of using the conventional power/ground plane pairs This along with current balancing can be used to manage return path discontinuities and power supply noise Many of the published work in this area have proved that the PTL concept is able to reduce SSN and enhance power and signal integrity Pseudo-balanced power transmission line (PB-PTL) concept has been shown to improve performance and reduce power consumption However, this has only been applied to relatively simple test vehicles In this paper, the PB-PTL scheme has been extended for driving multiple I/O drivers in field programmable gate array (FPGA) ICs This paper discusses the theory, simulation and measurement results for this implementation

Power integrity characterization and correlation of 3D package systems using on-chip measurements

Abstract: System power integrity characterization for low-power high-speed memory interface in a 3D package system is a challenging task due to probing difficulties imposed by small form factor. In this paper, power integrity measurements including supply noise, PSIJ sensitivity and PDN impedance curve using on-chip noise generator and monitors are presented. On-chip measurement data are validated by off-chip sense line measurements. Good correlations between simulation and measurements close the loop between analysis and verification for the system power supply delivery design.

Fundamentals of signal integrity

Abstract: A collection of slides from the authorpsilas seminar presentation is given. P/GBN is one of the key issues for designing high-speed digital circuit with good signal integrity (SI) and EMC performance. Several approaches to eliminate the P/GBN on the power delivery systems are investigated by both numerical simulations and experimental measurement.

Ball Grid Array package for automotive application: Strong link between design and 3D modeling

Abstract: High speed signals, design density, many power domains, product miniaturization and integration require high level of electrical, thermal and thermo-mechanical performances on each system component (IC-PKG-PCB). Ball Grid Array (BGA) package, thanks to design flexibility and wide substrate technology portfolio, is today a key part, highly challenging, of complex systems. This package is largely used also in automotive domain mainly for high-pin-count devices and in combination with Flip Chip (FC) technology for a direct and short device-to-substrate connection. In this work we describe design techniques and 3D modeling activity done to improve Power Integrity (PI), Signal Integrity (SI), thermal and thermo-mechanical behaviors of a complex FC-BGA automotive product using Cu pillar bumps and 4LY substrate as starting point. More than one thousand bumps and five hundred balls are the boundary conditions of the package connectivity. Step by step all design improvements are described: substrate stack-up modification, power and ground layers new sequence, device positioning analysis, SMD capacitors choice, placement and connection, vias number increase and pwr-to-gnd coupling maximization, top metal parasitics reduction by fan-in routing optimization on device area, planes integrity and layout improvement. Electrical, thermal and thermo-mechanical simulations, as fundamental part of design activity and performed through validated flows, demonstrate the improvement achieved. The strong link between design and modeling is today essential for first package success and, predicting `by design' potential issues and weaknesses, helps to reduce overall cost and development cycle time.

Analysis of SMT decoupling capacitor placement in electronic packages using hybrid modeling method

Abstract: An efficient hybrid modeling method is presented for analysis of the surface-mount technology (SMT) decoupling capacitor placement in the power distribution network (PDN) of an electronic package. The PDN includes the multilayered power-ground (P-G) planes, the P-G vias, and the decoupling capacitors to provide a low-impedance path between the printed circuit board and the die. The SMT decoupling capacitors are commonly used to mitigate the resonant phenomenon of the electronic package in cavity-like structure and provide the additional return paths for the signal traces. Applying the modal decomposition of the waves propagating inside the P-G planes and the traces, the electro-magnetic fields can be decomposed into the parallel-plate mode and the transmission-line mode. The former is analyzed by using the scattering matrix method for the finite P-G planes with multiple vias. The multiconductor transmission-line theory is applied to model the micro-striplines and striplines in the package. The method has been experimentally validated.