Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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20 May 2014
TL;DR: In this paper, the authors cover both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity, including simulations, numerical modelings and measurements for verification.
Abstract: Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep intoTSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered.
28 citations
TL;DR: In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented, and the results are validated with a place-and-route (P&R)-based physical implementation flow.
Abstract: In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.
27 citations
24 Jul 2006
TL;DR: A triangularization based structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid and achieves up to 133times and 109times speedup in macromodel building and simulation respectively.
Abstract: In this paper, a triangularization based structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is represented by interconnected basic blocks according to current density, and basic blocks are further clustered into compact blocks, each with a unique pole distribution. Then, the system is transformed into a triangular system, where compact blocks are in its diagonal and the system poles are determined only by the diagonal blocks. Finally, projection matrices are constructed and applied for compact blocks separately. The resulting macromodel has more matched poles and is more accurate than the one using flat projection. It is also sparse and enables a two-level analysis for simulation time reduction. Compared to existing approaches, TBS in experiments achieves up to 133/spl times/ and 109/spl times/ speedup in macromodel building and simulation respectively, and reduces waveform error by 33/spl times/.
27 citations
TL;DR: A power delivery monitor peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing enables rapid, automated analysis of supply impedance, as well as monitoring supply voltage droop of multi-core CPUs running full software workloads and during scan-test operations.
Abstract: This paper presents a power delivery monitor (PDM) peripheral integrated in a flip-chip packaged 28 nm system-on-chip (SoC) for mobile computing. The PDM is composed entirely of digital standard cells and consists of: 1) a fully integrated VCO-based digital sampling oscilloscope; 2) a synthetic current load; and 3) an event engine for triggering, analysis, and debug. Incorporated inside an SoC, it enables rapid, automated analysis of supply impedance, as well as monitoring supply voltage droop of multi-core CPUs running full software workloads and during scan-test operations. To demonstrate these capabilities, we describe a power integrity case study of a dual-core ARM Cortex-A57 cluster in a commercial 28 nm mobile SoC. Measurements are presented of power delivery network (PDN) electrical parameters, along with waveforms of the CPU cluster running test cases and benchmarks on bare metal and Linux OS. The effect of aggressive power management techniques, such as power gating on the dominant resonant frequency and peak impedance, is highlighted. Finally, we present measurements of supply voltage noise during various scan-test operations, an often-neglected aspect of SoC power integrity.
27 citations
TL;DR: This paper proposes a new frequency-domain PEEC solver which is based on the adaptive cross approximation and singular value decomposition, and a multiscale block decomposition is adopted to explicitly compute the inverse of the admittance matrix of the PEEC circuit.
Abstract: The solution of mixed electromagnetic/circuit problems is important for the electromagnetic compatibility/signal integrity/power integrity system designs. The ever-increasing frequency content of signals and decrease of geometrical features requires the 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, to be used for the analysis and design of high-speed circuits. Very large systems of equations are often produced and their efficient solution can be extremely challenging. In this paper, we propose a new frequency-domain PEEC solver which is based on the adaptive cross approximation and singular value decomposition. Taking advantage of the rank deficiency of the dense partial inductance and coefficient of potential matrices, a multiscale block decomposition is adopted to explicitly compute the inverse of the admittance matrix of the PEEC circuit. The proposed approach provides both speedup and memory storage saving, while preserving the accuracy. The efficiency of the proposed method is demonstrated through its application to the PEEC modeling of typical interconnect problems.
26 citations