Power integrity

About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.

Power integrity co-analysis and design in a PCB with BGA package using transmission matrix method

Abstract: Power integrity (PI) is among the main concerns in the design process of multilayer packages and printed circuit boards (PCBs) Based on Transmission Matrix Method (TMM), the PI performance of a Ball grid array (BGA) package mounted on a PCB is investigated in this paper The power/ground planes and the power/ground balls on a PCB and package are entirely equivalent to distributed RLGC circuits model and co-analyzed From this model, power performance could be computed with high efficiency Moreover, a design rule of power/ground balls arrangement is obtained by reducing the equivalent inductance and equivalent capacitance of BGA for good power integrity performance

Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs

Abstract: Power gating has been widely adopted in multicore designs The design of fast and reliable power mode transition for per-core power gating remains a challenging problem This paper studies the design methodology for fast power gating wake-up with guaranteed power integrity Two novel techniques, namely current shaping and multi-thread activation are proposed Models and physical implementation of both techniques are analyzed Experimental results demonstrated 15 to 11 times wake-up time speedup with no penalty on area or power consumptions by using the proposed techniques

Dealing with interconnect process variations

Abstract: Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including VIA, contact, metal, dielectric barriers and low-k dielectrics. Chemical Mechanical Polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered.

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill

Abstract: This paper introduces an anomaly detection methodology with machine learning for Circuit Probing (CP) using Integrated Passive Device (IPD) as example devices. The IPD can improve the power integrity, performance, and package dimensions of the Integrated Fan-Out Package on Package (InFO-PoP), which is more cost-effective than 3D Integrated Circuits (3DIC) to achieve “More than Moore’s law” for mobile devices. Because a defective IPD can invalidate the entire package, the previous test methods are dedicated to very high-end screening for the underkill/failure-escape of high quality and reliable devices. On the other hand, the overkill issues are not concerned yet, which periodically impact the yield and cost. In this paper, we propose a new flow with machine learning methodologies to detect previously ignored anomalies on site-aware wafer-maps for predictive maintenance. The proposed flow covers the overkill and re-test issues to complete the high-quality and cost-effective test methodology with test defense.

2.5D methodologies for electronic package and PCB modeling: Review and latest development

Abstract: This paper first surveys 2.5D methodologies, which are based on modal decomposition principle, for efficient modeling of electronic packages and multilayer printed circuit boards (PCB). It then reports the latest development of 2D discontinuous Galerkin method (2D DGTD) based 2.5D methodology for analysis of signal and power integrity in multilayer PCBs. Moreover, the recent study of handling narrow slots in the power-ground planes by a hybrid 1D- and 2D-DGTD method is also presented. Numerical examples are given with simulation results compared against measurement as well as full-wave simulation results.