Topic
Power integrity
About: Power integrity is a research topic. Over the lifetime, 983 publications have been published within this topic receiving 6867 citations.
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21 Nov 2007
TL;DR: In this paper, a two-dimensional full wave method for efficient power integrity and EMI analysis of general power/ground planes in high-speed electronic packages is developed, and the resultant equivalent magnetic source from the 2D simulation is used for EMI analyses via the free-space Green's function.
Abstract: We developed a two-dimensional full wave method for efficient power integrity and EMI Analysis of general power/ground planes in high-speed electronic packages. The resultant equivalent magnetic source from the 2D simulation is used for EMI analysis via the free-space Green's function. Both analytical and experimental validation shows that the method is accurate and efficient.
2 citations
25 Jul 2016
TL;DR: A novel testInterposer scheme composed of a test interposer and silicone rubber sheets is proposed for LPDDR4 memory test and is experimentally verified in time and frequency domains to prove their accuracy and practicality.
Abstract: Motivated by the increasing market demand for the high performance mobile devices, both the data rate and the number of pin of mixed-signal systems keep on increasing to realize multifunctional yet compact system designs. With this ascending technical trend, many signal integrity (SI) and power integrity (PI) problems such as ISI, jitter, crosstalk, simultaneous switching noise (SSN) have arisen that need to be thoroughly analyzed and tested. In order to accurately monitor the data signals of LPDDR4, a carefully designed test interposer considering such factors as impedance matching, minimization of skew and crosstalk needs to be proposed. In this paper, a novel test interposer scheme composed of a test interposer and silicone rubber sheets is proposed for LPDDR4 memory test. Through a series of simulations and measurements, we experimentally verify the proposed structures in time and frequency domains, and prove their accuracy and practicality.
2 citations
03 Apr 2005
TL;DR: In this article, a method for power integrity (PI) issue by using the isolation island and decoupling capacitors (de-caps) is presented, where the location of voltage regulator module (VRM) is taken into account.
Abstract: This paper presents a method for power integrity (PI) issue by using the isolation island and decoupling capacitors (de-caps). Deferent form the papers discussed before, the location of voltage regulator module (VRM) is taken into account. Without the de-caps, the fundamental resonant frequency is due to the two-dimensional cavity formed by power plan ground plane and VRM which can deteriorate the whole system. It can be shown that at the lower frequency, delta-I noise can be suppressed by VRM, but at the higher frequency, de-caps should be added to maintain the PI. Isolation island is used to help reducing the number of de-caps. The effects of different stick-ups are also discussed in this paper.
2 citations
01 Jun 2009
TL;DR: In this paper, the authors proposed a power plane applied spiral resonator to suppress GBN and SSN through very wideband from 0.22 GHz to 12.5 GHz under −25 dB.
Abstract: Using power plane applied spiral resonators, GBN and SSN can be suppressed through very wideband from 0.22 GHz to 12.5 GHz under −25 dB. Also, the designed spiral resonator is just located on the intersection between power plane and power via, and the diameter of resonator is 3 mm. Due to the localized small size of resonator, the degree of freedom for power plane design and signal integrity for guaranteed return current path are better than periodic EBG structure. Therefore, signal integrity and power integrity can be guaranteed in a low noise condition by using spiral resonator mounted power plane.
2 citations
01 May 2017
TL;DR: In this article, a new model is proposed to explain the effectiveness of decoupling capacitors in relation to their proximity to device power pins, which applies to power delivery networks (PDN) designed as parallel-plate power ground plane pairs.
Abstract: A new model is proposed to explain the effectiveness of decoupling capacitors in relation to their proximity to device power pins. The proposed approach applies to power delivery networks (PDN) designed as parallel-plate power ground plane pairs. The effectiveness of capacitors is explained through the device pin input impedance which can be expressed as a function of spatial coordinates. The proposed method conforms well to general observations and is validated by numerical examples.
2 citations